Nanomaterials-Based Charge Trapping Memory Devices

By Ammar Nayfeh and Nazek El-Atab

Rising consumer demand for low power consumption electronics has generated a need for scalable and reliable memory devices with low power consumption. At present, scaling memory devices and lowering their power consumption is becoming more difficult due to unresolved challenges, such as short channel effect, Drain Induced Barrier Lowering (DIBL), and sub-surface punch-through effect, all of which cause high leakage currents. As a result, the introduction of different memory architectures or materials is crucial.

Nanomaterials-based Charge Trapping Memory Devices provides a detailed explanation of memory device operation and an in-depth analysis of the requirements of future scalable and low powered memory devices in terms of new materials properties. The book presents techniques to fabricate nanomaterials with the desired properties. Finally, the book highlights the effect of incorporating such nanomaterials in memory devices.

This book is an important reference for materials scientists and engineers, who are looking to develop low-powered solutions to meet the growing demand for consumer electronic products and devices.

• Explores in depth memory device operation, requirements and challenges
• Presents fabrication methods and characterization results of new nanomaterials using techniques, including laser ablation of nanoparticles, ALD growth of nano-islands, and agglomeration-based technique of nanoparticles
• Demonstrates how nanomaterials affect the performance of memory devices

• Language: English
• Publisher: Elsevier Science
• Release date: May 27, 2020
• ISBN: 9780128223437

Ammar Nayfeh

Professor Ammar Nayfeh was born in Urbana IL in 1979. He received his bachelor's degree from the University of Illinois Urbana Champaign in 2001 in electrical engineering and his master's degree in 2003 from Stanford University. Dr. Nayfeh earned a Ph.D. in electrical engineering from Stanford University in 2006. His research focused on heteroepitaxy of germanium on silicon for electronic and photonic devices. After his PhD, he joined Advanced Micro Devices as a researcher working in collaboration with IBM. After that he joined a silicon valley startup company, Innovative Silicon (ISi) in 2008. In addition, he was a part time professor at San Jose State University. In June 2010, he joined MIT as a visiting scholar and became a faculty member at the Masdar Institute currently Khalifa University. His research interest focuses on nanotechnology for future more efficient low power electronic and photonic devices. Professor Nayfeh is currently an associate professor in the Department Electrical Engineering and Computer Science (EECS) at Khalifa University. Professor Ammar Nayfeh has authored or co-authored over 100 publications, and holds three patents. He is a member of IEEE, MRS and Stanford Alumni Association. He has received the Material Research Society Graduate Student Award, the Robert C. Maclinche Scholarship at UIUC, and Stanford Graduate Fellowship.

Book preview

Nanomaterials-based Charge Trapping Memory Devices

Micro and Nano Technologies

Ammar Nayfeh

Nazek El-Atab

Contents

Cover

Title page

Copyright

Preface

1: Basics of memory devices

Abstract

1.1. Flash memory cells overview

1.2. Challenges and requirements of current memory devices

2: Overview of charge trapping memory devices—Tunnel band engineering

Abstract

2.1. Tunnel oxide engineering

3: Overview of charge trapping memory devices—charge trapping layer engineering

Abstract

3.1. Charge trapping layer engineering

4: Atomic layer deposition based nano-island growth

Abstract

4.1. Atomic layer deposition overview

4.2. Growth mechanisms

4.3. Nano-islands growth by ALD

4.4. Memory device with zirconia nano-islands

4.5. Memory device with ZnO nano-islands

5: Laser ablated nanoparticles synthesis

Abstract

5.1. Laser ablation overview

5.2. Laser ablated Si nanoparticles

5.3. Si-nanoparticles charge trapping layer

5.4. Si-nanoparticles charge trapping layer

6: Agglomeration-based nanoparticle fabrication

Abstract

6.1. ZnO nanoparticles coating overview

6.2. Electronic and optical characterization of ZnO agglomerations

6.3. Conclusion

7: Scalability of nano-island based memory devices

Abstract

7.1. ITRS roadmap for memory devices

7.2. Scalability study

7.3. Limitations of planar flash memory

7.4. From planar to 3D NAND [from thesis]

7.5. Limitations of 3D NAND [from thesis]

Index

Copyright

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ISBN: 978-0-12-822342-0

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Preface

A marriage between nanotechnology and traditional electrical semiconductor-based devices is vital for the future progress. Currently, nanotechnology is no longer a pipe dream, or a catchy phrase but now it has real-life applications in the main stream. In 2019, you can buy a TV with a quantum dot displays or buy makeup that has nanomaterials to name a few. While some nanodreams are still not real, like time traveling in the quantum realm with Pym particles as the Avengers did to defeat Thanos or using nano to cure cancer, it is clear that nanotechnology is very relevant now and a key to future. It is important that current and future graduate students are educated in the area of nanomaterials as this will be a key tool for them. Specifically in the area of the electronics, nanotechnology will play a vital role in the ability to increase device performance. The human demand for faster, more efficient, and smaller devices is continuing and will not stop in the foreseeable. As a result, more efficient devices are needed. One critical component is the future of memory devices. Traditional memories have reached a brick wall so to speak and only incremental improvements can be done. The major breakthroughs will arise with new nanomaterials and devices. The question is, how can nanotechnology be used to improve memory devices? In this book, we highlight the use the nanomaterials in memory and how they can be used to improve their performance.

Over the last four decades we have seen tremendous growth in semiconductor electronics. This growth has been fuelled by the matured complementary metal oxide semiconductor (CMOS) technology. Its benefits have been enjoyed by us through information technology. From computation to communication to infotainment, in every electronics and gadgets, CMOS technology-enabled memory devices have penetrated in a pervasive manner. Going forward, with rising consumer demand on low-power consumption electronics, scalable, and reliable memory device with low-power consumption are needed. Currently, further scaling the memory devices and lowering their power consumption is becoming more difficult due to different unsolved problems such as short-channel effect, Drain Induced Barrier Lowering (DIBL), and sub-surface punch-through effect which cause high-leakage currents. As a result, the introduction of different memory architectures or materials is crucial. In this book, we will provide a detailed explanation of memory devices operation and an in-depth analysis of the requirements of future scalable and low-power memory devices in terms of new materials properties. We will then present different techniques to fabricate such nanomaterials with the desired properties (fabrication and characterization results will be shown). Finally, we will show the effect of incorporating such nanomaterials in memory devices and we will provide physics-based explanation of the performance of these devices.

Graduate students and researchers (both in academia and industry) who are willing to learn about the latest findings related to low-power memory devices usually seek research journal papers and conference proceedings related to the topic. These journal papers about latest memory devices with novel nanomaterials usually do not include the fabrication technique and characterization results of the nanomaterials, therefore, the readers will have to check other papers and books about the fabrication techniques. And to understand the operation of such memory devices, researchers need to find and read books about semiconductor devices. In this book we provide an in-depth explanation of memory devices and their latest requirements and challenges. We also provide a detailed explanation of the fabrication process of different novel nanomaterials using different technique. Finally, we show the effect of the incorporation of such nanomaterials in memory devices on their performance.

The three key features in our book include:

1. A detailed analysis and explanation of memory devices operation, requirements, and challenges

2. The fabrication method and characterization results of new nanomaterials using different techniques (laser ablation of nanoparticles, ALD growth of nano-islands, agglomeration-based technique of nanoparticles, etc.). The nanomaterials will be characterized using different tools such as AFM, TEM, UV-Vis-NIR spectrophotometer, XPS, etc. Our aim is to show that such nanomaterials are promising in future low-power memory devices.

3. The incorporation of nanomaterials in memory devices and their effect of the performance of the devices.

First and foremost I would like to thank Allah (God) for his guidance and wisdom in helping us to put this book together. This book was a culmination of work that started with Dr. Nazek El-Atab who I had the pleasure of advising as PhD student. Her hard work, motivation, and excellence was the driving force of this book. It was an honor and pleasure to put this book together with Dr. El-Atab.

In addition it would not be possible without the full support of Khalifa University and the leadership in the UAE. For that I thank them greatly. I would also like to thank my parents Professor Munir and Hutaf Nayfeh for their love and support and for giving me the means to achieve this. Last but not least, I would like to thank greatly my loving wife, Lama and children Laith, Leia, and Zaid. Without their unconditional love and constant support this book would not be possible.

– Prof. Ammar Nayfeh

My deepest gratitude goes to my advisor, Prof. Ammar Nayfeh. He was involved in every aspect of my research and I would not have excelled without his endless support and wise decisions. I feel enormously fortunate to have worked with the finest advisor that one could possibly hope for. In addition, no words would ever do justice to express my sincere appreciation to my most wonderful family and husband, Saadeddine. Their unconditional love, support, encouragement, and sacrifice have allowed me to chase my ambition and realize this book.

– Dr. Nazek El-Atab

1

Basics of memory devices

Abstract

Memory devices are considered to be the building block in almost all of the modern electronic applications from cell phones to laptops, smart televisions, automotive systems, etc. In this chapter, an overview of flash memory that includes the structure and operation are first presented, with a focus on charge trapping memory type. Following the overview, the requirements for the different layers in the active region of the memory, to extend their scalability, are discussed.

Keywords

memory devices

tunnel oxide

blocking oxide

charge trapping layer

high-κ

1.1. Flash memory cells overview

In the past decade, memory chips with low cost and low power consumption have gained more attention due to the growing market of consumer electronic equipment such as digital cameras and cellular phones. Moreover, the demand for memories with higher density is expected to increase. From a device perspective, increasing the density has made the scaling of flash memory devices possible. Fig. 1.1 shows how the flash memory has scaled by a factor of 1000 during the period from 1986 to 2006 to reach 65 nm. In the past, it was easier to scale these devices. Currently, scaling the flash memory devices beyond the 32 nm technology node (depending on NAND or NOR structure) is becoming more difficult due to different unsolved problems such as short channel effect, drain induced barrier lowering (DIBL), and sub-surface punch-through effect which cause high leakage currents.

Figure 1.1   Flash memory scaling history. Obtained from ITRS.

Namely, the scaling of CMOS logic device is far ahead of the semiconductor flash memory. In 2001, the minimum feature size of a single CMOSFET has reduced to 15 nm with an equivalent gate oxide thickness (EOT) of 0.8 nm [1]. However, for semiconductor flash memories, the EOT of the tunnel oxide (TO) is still larger than 6–8 nm. Moreover, the required operation voltage of semiconductor flash memory is still higher than 10 V, while the CMOS logic operation voltage has been reduced to around 1 V.

It is essential to scale down the EOT of the gate stack in order to obtain a small memory cell size, and extend the battery life. In fact, there is a relation between the operation voltage of semiconductor flash memory devices and the gate stack scaling. In order to meet the 10 years data retention requirement in the commercial flash memory chip, a TO thickness of more than 8 nm is presently used. The operation voltage can be scaled down from 10 to about 4 V if the TO thickness was made thinner than 2 nm, however, the retention time would be reduced from 10 years to several seconds [2].

Silicon-oxide-nitride-oxide-silicon (SONOS) memories were then introduced as an improved version of flash memories. Actually, SONOS has a very similar structure to the standard double poly-silicon flash memory but with a Si3N4 charge-trapping layer replacing the poly-silicon. SONOS offers higher quality storage because Si3N4 film is homogeneous unlike the poly-silicon which has small irregularities. Also, SONOS is considered a lower cost version of flash memory because its oxide layering can be fabricated easily on the existing lines and can be easily combined with CMOS logic, however, flash memory requires the production of a high-performance insulating barrier on the gate leads of its transistors which leads to about nine additional fabrication steps [3].

Moreover, the charge-trapping layer of the SONOS structure is nonconductive which means that a shorting defect in the oxide will only affect a localized area of charge. This differs from flash memory with poly-silicon where the short would be considered as a single point of failure. SONOS memory is also more scalable and has a lower operating voltage of 8–12 V [4].

However, the scaling and operating voltage of SONOS is still not comparable with those of CMOS logic. Most of the scaling restrictions are now governed by the device structure and the materials used. Therefore, there is a need to seek novel materials and memory structures to enable the reduction of the operation voltage without compromising the retention time characteristic by using new materials and structures for the channel, charge trapping layer, and TO layer.

1.1.1. Basic nonvolatile memory cell structure

The operation of the memory is based on three different processes: programming the memory to store some data, retaining the data, and retrieving the data by reading the state of the memory [5].

The structure of current memory devices is based on the metal-oxide-semiconductor field-effect-transistor (MOSFET) structure as shown in Fig. 1.2. The MOSFET based memory has an additional layer embedded within the gate oxide to store the data. Based on the type of this additional layer, two kinds of memory cells can be realized: Floating gate (FG) based memory, which was first demonstrated by Guterman et al. [2] and charge trapping (CT) memory. In the floating gate memory, highly doped poly-silicon is used to store the information while in the charge trapping memory devices, the storage layer consists of a non-conductive material, and nitride or oxy-nitrides are conventionally used. On the other hand, the charge trapping memory, shown in Fig. 1.2, employs a dielectric layer which is conventionally based on silicon nitride (Si3N4). The first memory cell employing Si3N4 as a charge trapping material was demonstrated in 1967 [2]. The charge trapping memory based on as poly-Si/oxide/Si3N4/oxide/Si substrate is generally known as SONOS. Both floating gate and charge trapping layers are embedded between two dielectric layers: the bottom oxide known as the TO is traditionally based on silicon dioxide, while the upper oxide can differ based on the device type. Specifically, in the case of a floating gate memory, the upper oxide is based on a stack of SiO2/Si3N4/SiO2 (ONO) and is known as the interpoly dielectric (IPD) or inter-gate dielectric (IGD), whereas in charge trapping memory devices, the upper oxide is based on a SiO2 layer known as the blocking oxide (BO). The TO and BO are used to avoid charge leakage to the Si channel and the gate and maintain good gate control over the device. The material used for the TO and BO was initially SiO2 due to the good quality of the interface with Si, however, currently Al2O3 is being employed to avoid charge leakage with scaling of the flash memory. In addition, other higher-κ oxides are being studied to enable further scaling of the memory as will be explained in Section 1.2.

Figure 1.2   Cross-sectional illustration of a MOSFET based nonvolatile memory.

Based on the ITRS projections for memory devices, the charge trapping memory is considered as the most promising and practical device especially for NAND structures [6].

In brief, in charge trapping memory devices:

• The charges are stored in charge trapping states in a dielectric as opposed to a conductive semiconductor in floating gate memory.

• The lithographic definition of a floating gate is not required during the process flow. The gate oxide consists of three layers of dielectrics embedded between the channel and the gate. The gate oxide stack is more scalable compared to the floating gate memory, and therefore, the program/erase voltage will be more scalable.

• Cell-to-cell capacitive interferences are greatly reduced. This is because the charge-trapping layer is a thin dielectric material (∼ 5 nm) instead of the very thick semiconductor (∼ 70 nm) used in floating gate memory.

Thus, in this book the focus will be on the scalability of charge trapping memory type using new materials.

1.1.2. Basic nonvolatile memory cell operation

The data is stored in the floating gate or charge trapping layers as electric charges, which can modify the threshold voltage (Vt) of the memory devices. To program the memory requires introducing electrons into the charge storage layer through the TO. This leads to a shift in the Vt of the memory cell toward the positive direction. Whereas in order to erase the memory, the stored charges are ejected from the floating gate or charge trapping layer back into the substrate resulting in a Vt shift toward the negative direction.

During the read operation of the state of the memory, a gate voltage is applied which falls in between the Vt of both the programmed and erased states and is known as VRead, while the current is detected and measured. The level of the measured current specifies if the device is in state 1 (also known as erased state), or in state 0 (i.e., programmed state). In fact, this takes place in a single level cell (SLC) memory, as depicted in Fig. 1.3A, where only 1 bit can be stored with two allowed states. When the shift in threshold voltage between both programmed and erased states is wide enough and the retention characteristic is decent, then it becomes possible to store multiple bits in multi-level cells (MLC) [2]. For instance, a MLC can store up to 2 bits/cell which indicates that four distinct storage states can be saved: 00, 01, 10, and 11, as depicted in Fig. 1.3B. Similarly, three-level cell (TLC) devices can store up to 3 bits/cell with 8 distinct storage levels [7].

Figure 1.3   (A) Memory states in a 1 bit storage single level cell (SLC) and (B) Memory states in a 2 bits multi-level cell (MLC).

In Fig. 1.3, the gap shown in between the different storage levels is the margin across which we can apply the VRead to read the state of the memory. As long as the different storage levels do not overlap with the read voltages, the stored data can be read and accessed correctly. In addition, the larger the margin between the stored levels, the larger the program/erase (P/E) cycles that can be applied before the device fails. Each P/E cycle slightly deteriorates the TO which causes an increase in the probability of electrons trapping within the oxide. This weakening of the TO modulates the threshold voltage of the transistor, which results in shifting the bits placements and thus leading to a failure in reading the correct state of the memory. The cost per bit is lower for the MLC device compared to the SLC memory. Nevertheless, the writing speed in MLC is slower, in addition, since the MLC shows a larger error rate in reading the state of the devices, this necessitates a stronger error correcting code to be executed. SLC memory devices are still favored especially in applications where the speed and reliability of the device are more imperative than capacity.

Therefore, during the program operation of the memory, when applying a positive gate bias, charges in the channel gain enough energy and get