Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

By Chenming Hu, Sourabh Khandelwal, Yogesh Singh Chauhan and 5 more

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design helps readers develop an understanding of a FDSOI device and its simulation model. It covers the physics and operation of the FDSOI device, explaining not only how FDSOI enables further scaling, but also how it offers unique possibilities in circuits. Following chapters cover the industry standard compact model BSIM-IMG for FDSOI devices. The book addresses core surface-potential calculations and the plethora of real devices and potential effects. Written by the original developers of the industrial standard model, this book is an excellent reference for the new BSIM-IMG compact model for emerging FDSOI technology.

The authors include chapters on step-by-step parameters extraction procedure for BSIM-IMG model and rigorous industry grade tests that the BSIM-IMG model has undergone. There is also a chapter on analog and RF circuit design in FDSOI technology using the BSIM-IMG model.

• Provides a detailed discussion of the BSIM-IMG model and the industry standard simulation model for FDSOI, all presented by the developers of the model
• Explains the complex operation of the FDSOI device and its use of two independent control inputs
• Addresses the parameter extraction challenges for those using this model

• Language: English
• Publisher: Elsevier Science
• Release date: May 21, 2019
• ISBN: 9780081024027

Chenming Hu

Chenming Hu is Distinguished Chair Professor Emeritus at UC Berkeley. He was the Chief Technology Officer of TSMC and founder of Celestry Design Technologies. He is best known for developing the revolutionary 3D transistor FinFET that powers semiconductor chips beyond 20nm. He also led the development of BSIM-- the industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. His honors include the Asian American Engineer of the Year Award, IEEE Andrew Grove Award and Solid Circuits Award as well as Nishizawa Medal, and UC Berkeley's highest honor for teaching-- the Berkeley Distinguished Teaching Award.

Book preview

Industry Standard FDSOI Compact Model BSIM-IMG for IC Design

Edited by

Chenming Hu

Sourabh Khandelwal

Yogesh Singh Chauhan

Thomas Mckay

Josef Watts

Juan Pablo Duarte

Pragya Kushwaha

Harshit Agarwal

Table of Contents

Cover image

Title page

Copyright

List of Contributors

Chapter 1. Fully-Depleted Silicon on Oxide Transistor and Compact Model

Abstract

1.1 Silicon on Oxide and Pre-2010 SOI CMOS Transistor

1.2 What Limits the Scaling of the Bulk and PDSOI CMOS Transistors?

1.3 The Ultrathin-Body Concept and Ultrathin-Body Fully Depleted SOI

1.4 Comparison of FDSOI with FinFET and Other Ultrathin-Body Transistors

1.5 Compact Model—The Bridge Between FDSOI Device/Technology and IC Design

References

Chapter 2. Core Model for Independent Multigate MOSFETs

Abstract

2.1 Introduction

2.2 Independent Multigate MOSFETs

2.3 Core Model

2.4 Core Model Analytical Solution

2.5 Drain Current Model

2.6 Terminal Charge Model

References

Chapter 3. Channel Current Model With Real Device Effects in BSIM-IMG

Abstract

3.1 Introduction

3.2 Vertical Field Dependence of Carrier Mobility

3.3 Threshold Voltage

3.4 Drain Saturation Voltage

3.5 Quantum Mechanical Effects

3.6 Lateral Nonuniform Doping Model

3.7 Output Conductance Model

3.8 Velocity Saturation Effect

3.9 Series Resistance Model

3.10 Channel Current Expression

References

Chapter 4. Leakage Current and Thermal Effects

Abstract

4.1 Leakage Currents and Their Modeling

4.2 Thermal Effects and Their Modeling

References

Chapter 5. Model for Terminal Charges and Capacitances in BSIM-IMG

Abstract

5.1 Introduction

5.2 Capacitance Calculation From Terminal Charges

5.3 Intrinsic Terminal Charge Model in BSIM-IMG

5.4 Modeling the Impact of Real Device Effects on Terminal Charges

5.5 Extrinsic Capacitance Model in BSIM-IMG

References

Chapter 6. Parameter Extraction With BSIM-IMG Compact Model

Abstract

6.1 Background

6.2 Extraction of Large-Sized Device Parameters

6.3 Short-Channel Device Extraction and Length Scaling

6.4 Leakage Current Extraction

6.5 Extraction of Temperature Dependence Parameters

References

Chapter 7. Testing BSIM-IMG Model Quality

Abstract

7.1 Symmetry Tests

7.2 Weak and Strong Inversion Test

7.3 Test for Self-Heating Effect

7.4 Model Validation With Germanium on Insulator FD-SOI Transistor

References

Chapter 8. High-Frequency and Noise Models in BSIM-IMG

Abstract

8.1 Radio-Frequency Characterization

8.2 Radio-Frequency Modeling and Parameter Extraction

8.3 Noise Models

8.4 Thermal Noise Characterization

8.5 Model Validation

8.6 Induced Gate Thermal Noise Model

8.7 Appendix

References

Chapter 9. FDSOI Industry Perspective and Analog/Radio-Frequency Circuit Design

Abstract

9.1 Using the Model in an Industrial Process Design Kit

9.2 FDSOI Technology Figures of Merit

References

Index

Copyright

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List of Contributors

Harshit Agarwal,     Center Manager and Postdoctoral Researcher, Berkeley Device Modeling Center, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States

Huan-Lin Chang,     Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Yogesh Singh Chauhan

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Associate Professor, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India

Juan Pablo Duarte,     Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Chenming Hu

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Professor of the Graduate School, University of California, Berkeley, CA, United States

Sourabh Khandelwal

Macquarie University, Macquarie Park, New South Wales, Australia

Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Research Faculty, University of South Florida, Tampa, FL, United States

Pragya Kushwaha,     Postdoctoral Researcher, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, United States

Yen-Kai Lin,     Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, United States

Thomas McKay,     GlobalFoundries, Santa Clara, CA, United States

Chapter 1

Fully-Depleted Silicon on Oxide Transistor and Compact Model

Chenming Hu,    Professor of the Graduate School, University of California, Berkeley, CA, United States

Abstract

This chapter explains why the limits of scaling faced by the bulk planar MOS transistors can be overcome with the ultra-thin-body transistor structures, of which the fully-depleted silicon-on oxide (FDSOI) is one and the FinFET is another. It also explains what constitutes a good compact model and the role that the BSIM models play in the semiconductor industry.

Keywords

Silicon on oxide; CMOS transistor; IC design; wafer; ultrathin body; compact model; FDSOI; BSIM

1.1 Silicon on Oxide and Pre-2010 SOI CMOS Transistor

Silicon on oxide (SOI) refers to a special type of silicon substrates (wafers) that IC manufacturers purchase from a few SOI wafer manufacturers. (The simple silicon wafer is sometimes called the bulk silicon wafer to distinguish it from SOI.) An SOI wafer consists of a thick Si substrate that provides mechanical rigidity, a buried oxide (typically 10–200 nm thick), and a second top silicon layer (10–100 nm thick). The transistors and circuits are fabricated in the top Si layer, and its quality and uniformity is of the ultimate importance. Sometimes, the term SOI is used to refer to the top silicon film itself as well as the film/oxide/substrate combination.

Fig. 1.1 shows the steps of making an SOI wafer (Celler, George, and Michael Wolf. Smart Cut A Guide to the Technology, the Process, the Products, SOITEC. July 2003). Step 1 is to implant hydrogen into a silicon wafer that has a thin SiO2 film at the surface. The hydrogen concentration peaks at a distance D below the surface. Step 2 is to place the first wafer, upside down, over a second plain wafer. The two wafers adhere to each other by the chemical bonding force. A low-temperature annealing causes the two wafers to fuse together. Step 3 is to apply another annealing step that causes the implanted hydrogen to coalesce and form many tiny hydrogen bubbles at depth D. This creates sufficient mechanical stress to break the wafer at that plane. The final step, Step 4, is to polish the surface. Now the SOI wafer is ready for use. The Si film is of high quality and suitable for IC manufacturing. Fig. 1.2 shows the cross-sectional SEMs of two SOI transistors.

Figure 1.1 Steps of making an SOI wafer.

Figure 1.2 Cross section of two SOI transistors. The lower structures are the transistors and contacts. The upper structures are the interconnect lines and vias.

Before 2010 SOI complementary metal-oxide-semiconductor (CMOS) employed SOI wafers with relatively thick (>30 nm) and relatively heavily doped silicon film. The combination of the Si film thickness and doping makes the depletion layer under that transistor channel thinner than the Si film thickness. This condition is called partial depletion, and the technology is known as partially depleted SOI (PDSOI). The alternative, a technology employing a thinner and lightly doped (or undoped) Si film, is known as fully depleted SOI (FDSOI) because the film is fully depleted under the transistor channel. It is interesting to note that the PDSOI designation was proudly highlighted by the SOI CMOS manufacturers in the 15 years prior to 2010 because it was known that FDSOI had worse short-channel effects [1] than PDSOI due to the elimination of the beneficial background plane effect provided by the undepleted body [2]. Today’s understanding is exactly the opposite—FDSOI provides superb short-channel behaviors. What changed the understanding is part of the story that this chapter will tell.

A PDSOI transistor is basically identical to a bulk transistor except that it is fabricated in a silicon island surrounded by oxide on the bottom and on the four sides. It can be scaled to the same gate length as the bulk transistor. However, it provides faster circuit speeds because the source/drain bottom to body junction capacitance is eliminated as the source/drain diffusion regions extend vertically to the buried oxide. Another source of speed advantage is that the SOI transistor has less body effect (its threshold voltage does not raise as much as in bulk transistor when the source voltage rises). Because the SOI transistor is in a silicon island, its body (the silicon above the buried oxide and bounded by oxide trench isolation on two sides and by source/drain junctions on the two other sides) is electrically floating, not grounded as in a bulk transistor. The potential of the floating body can float up and down with the source voltage, so the source to body voltage, Vbg, is reduced in comparison to bulk transistor. Body effect reduces the on-state current of the transistors that are stacked in series in a multiple fan-in logic gates. Less body effect means faster logic gates. These benefits over the bulk transistor are retained in the post-2010 FDSOI, which also allows scaling beyond the limit of bulk transistor as explained in the next sections.

1.2 What Limits the Scaling of the Bulk and PDSOI CMOS Transistors?

The continuing reduction of transistor and circuit sizes has led to steady improvements in the cost, speed, and power consumption of integrated circuits. Another part of the semiconductor industry’s formula for success has been keeping changes incremental, not drastic. The planar bulk metal-oxide-semiconductor transistor (MOSFET) served the electronics industry well for 40 years through 2010. Aggressive engineering had managed to reduce the transistor gate length, gate oxide thickness, etc. again and again without changing the transistor’s basic structure. The widely accepted transistor scaling rules held that the transistor gate length scaling would end when gate oxide thickness, the source/drain junction depth, or channel doping concentration could not be scaled any more. By the end of the 1990s, it was clear to all that all those three technology parameters would end and prevent COMS scaling from going beyond 30 nm.

It is now known that none of the three parameters would prevent the achievement of single-digit-nm MOSFET with good short-channel behaviors—good subthreshold swing, low Vt sensitivity to Lg and Vd, and low leakage current. What was missed earlier was the supreme importance of the transistor body thickness.

Fig. 1.3 explains the root cause of the escalating short-channel problem in the 20th-century MOSFETs [3]. A transistor is turned on and off when Vg lowers and raises the potential barrier between the channel and the source through the gate-to-channel capacitance, Cg. In an ideal transistor the channel potential is only controlled by Vg through Cg. In a short-channel transistor the channel potential is also subject to the influence of Vd through Cd. When Lg is large, Cd is much smaller than Cg, and the drain voltage does not compete with Vg as the sole controlling voltage. As Lg decreases, Cd increases, and Vd can act as a second gate in that it has control over the channel just like a gate. In extreme cases, Vg has less control than Vd, and the transistor can be turned on by Vd alone without Vg and log (Id) versus Vg would be a very flat line. Before reaching that extreme, we get increasingly worse subthreshold swing and Vt sensitivity to Vd and Lg, all leading to large leakage current and power consumption. The solution that worked well in the 20th century was to increase Cg by reducing the gate oxide thickness in proportion to Lg.

Figure 1.3 With decreasing L, rising Cd allows Vd to control the channel potential (lower figure) just as Vg [3]. Scaling the gate oxide thickness was a good solution for this problem in the 20th century.

However, bulk MOSFET Lg scaling would not have continued even if an ideal zero thickness dielectric were available. Fig. 1.4 shows that the source to drain leakage current does not have to flow along the silicon-dielectric interface. Leakage paths nanometers below the interface, illustrated in Fig. 1.4, are more problematic than the surface leakage path because they are separated from the gate electrode by a large distance even if the gate oxide were 0 nm thin. In other words the gate and Vg have only weak control over the potential barrier along these subinterface paths. Therefore the imaginary 0 nm gate oxide would not have helped much with transistor scaling.

Figure 1.4 With very short Lg, even a ~0 nm thin gate dielectric cannot ensure that the gate is closer to (and thus have more control over) the leakage current than the drain because the leakage current paths can be several nanometers below the interface [3].

1.3 The Ultrathin-Body Concept and Ultrathin-Body Fully Depleted SOI

Based on the understanding of the root cause, researchers at UC Berkeley proposed an ultrathin-body (UTB) scaling concept and two structures that implement the concept to US government’s DARPA (Defense Advanced Research Project Agency) in response to its request for proposal for sub-25 nm switching devices in 1996. The two proposed thin-body implementations were UTB (FD)SOI and FinFET. By 2000 we successfully demonstrated both implementations and showed that they both can achieve excellent short-channel leakage current [4,5]. By 2002 the International Technology Roadmap of Semiconductors listed these two transistor structures as the only successors to the bulk planar transistor. Today all sub-20 nm CMOS technologies are based on these two transistor structures. This chapter will focus on the FDSOI.

Fig. 1.5 illustrates a generic UTB MOSFET. The deepest possible leakage path is at the bottom of the thin body. There are no leakage paths far from the gate like those shown in Fig. 1.4—if the body is thin enough. The bottom of the body (the worst leakage path) is electrostatically separated from the gate by the sum of the body thickness, Tsi, and Tox (εsi/εox). When Lg is equal to twice this sum, the drain and the gate are at equal electrical distance from the midpoint between source and drain at the bottom of the body. Therefore the drain and the gate have roughly equal electrostatic control over the leakage. So, to ensure that the gate has the dominant control of the leakage over the drain, Tsi must be significantly less than Lg/2, say Lg/4 [5]. The UTB concept leads to a new scaling rule: while Tox (εsi/εox) is saturating at 0.5 nm, Lg can be reduced as long as Tsi can be reduced to satisfy.

(1.1)

Figure 1.5 Top: A sufficiently thin Si body eliminates the leakage paths that are far from the gate in Fig. 1.4. Therefore the gate (Vg) dominates over the drain (Vd) in determining the leakage current [3].

Fig. 1.6 shows the cross section of an FDSOI with 25 nm Lg. It also shows the simulated Id versus Vg for three different Tsi. In all three cases the undoped body is fully depleted. The top curve is for Tsi=8 nm, and the swing is poor, and the leakage is unacceptable. The middle curve is for Tsi=6 nm, and the swing is better and Ioff is about 100× lower than the 8 nm body device. The bottom curve is for Tsi=4 nm. In this case, Ioff is superbly low, about another 100× lower than the 6 nm body case. Clearly, we are looking at a new regime of SOI MOSFET. In this UTB regime, every 1 nm reduction of body thickness can reduce Ioff by an order of magnitude. Therefore the structure is called UTB-SOI transistor [5]. The UTB is the cause of the superb behavior of the short-channel transistor. There is no cause–effect relationship