Learning from VLSI Design Experience

By Weng Fook Lee

This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.

• Language: English
• Publisher: Springer
• Release date: Dec 14, 2018
• ISBN: 9783030032388

Book preview

© Springer Nature Switzerland AG 2019

Weng Fook LeeLearning from VLSI Design Experience https://doi.org/10.1007/978-3-030-03238-8_1

1. Introduction

Weng Fook Lee¹ 

(1)

Emerald Systems, Bayan Lepas, Malaysia

In today’s growth of mobile smartphones, tablets, lightweight laptops, and ultrabooks, complex and powerful IC chips are used extensively in almost every aspect of our daily lives. With smartphones reaching one billion units a year, complex design of System on Chip (SoC) and application-specific integrated circuit (ASIC) are driven with more features and capabilities. The increased functionality and features increase design complexity at a scale unseen before in the field of very-large-scale integration (VLSI) design.

Design of ASIC and SoC with millions of transistors poses a difficult challenge in VLSI design. Some complex advanced ASIC or SoC used in gaming console surpass one billion transistor count. Verification of such chips becomes a difficult task, with design bugs needed to be caught prior to design tapeout.

Fabrication cost of VLSI chips is very high; any design bugs caught in silicon after fabrication would require design fixes and fabrication respin, increasing the financial cost to bring the chip to the market.

Design of ASIC and SoC is complex and difficult. Verification of multimillion transistor design is equally as complex. Effective and efficient design methodology is needed to aid the design of ASIC and SoC. This book shares the design knowledge gained by experienced designers, covering design methodology, multi-clock design, latch inference, scan chain, ATPG, logic BIST, memory BIST, signed Verilog, state machine, common RTL coding rules, and code coverage.

© Springer Nature Switzerland AG 2019

Weng Fook LeeLearning from VLSI Design Experience https://doi.org/10.1007/978-3-030-03238-8_2

2. Design Methodology and Flow

Weng Fook Lee¹ 

(1)

Emerald Systems, Bayan Lepas, Malaysia

All integrated circuits (IC) are designed using a predefined flow and methodology. This flow and methodology allow the design engineer to follow each step of the flow and to take the appropriate action along the flow to address any problems that arise.

Design methodology and flow can be categorized into three distinct flow, analog/custom design flow, digital design flow, and mixed signal design flow. Each flow is catered to its particular design, such as analog/custom design flow for analog/custom circuits. Similarly digital design flow is used for digital design and mixed signal design flow for mixed signal