Nanoelectronics: Devices, Circuits and Systems

By Elsevier Science

Nanoelectronics: Devices, Circuits and Systems explores current and emerging trends in the field of nanoelectronics, from both a devices-to-circuits and circuits-to-systems perspective. It covers a wide spectrum and detailed discussion on the field of nanoelectronic devices, circuits and systems. This book presents an in-depth analysis and description of electron transport phenomenon at nanoscale dimensions. Both qualitative and analytical approaches are taken to explore the devices, circuit functionalities and their system applications at deep submicron and nanoscale levels. Recent devices, including FinFET, Tunnel FET, and emerging materials, including graphene, and its applications are discussed.

In addition, a chapter on advanced VLSI interconnects gives clear insight to the importance of these nano-transmission lines in determining the overall IC performance. The importance of integration of optics with electronics is elucidated in the optoelectronics and photonic integrated circuit sections of this book. This book provides valuable resource materials for scientists and electrical engineers who want to learn more about nanoscale electronic materials and how they are used.

• Shows how electronic transport works at the nanoscale level
• Demonstrates how nanotechnology can help engineers create more effective circuits and systems
• Assesses the most commonly used nanoelectronic devices, explaining which is best for different situations

• Language: English
• Publisher: Elsevier Science
• Release date: Oct 5, 2018
• ISBN: 9780128133545

Book preview

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Part I

Device Modeling and Applications

Outline

Chapter 1 Tunnel FET: subtitle

Chapter 2 Electrothermal Characterization, TCAD Simulations, and Physical Modeling of Advanced SiGe HBTs

Chapter 3 InP-Based High-Electron-Mobility Transistors for High-Frequency Applications

Chapter 4 Organic Transistor- Device Structure, Model and Applications

Chapter 1

Tunnel FET

Devices and Circuits

Prabhat Kumar Dubey,    Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand, India

Abstract

The superiority of the metal oxide semiconductor field-effect transistor (MOSFET) device over other devices lies in the scalability of these devices. However, the channel length scaling of MOSFETs has resulted in enormous energy dissipation in conventional complementary metal oxide semiconductor technology. It means, successive technologies cannot be continued with scaling of the MOSFETs for improved performance. Therefore, transistors with reduced energy dissipation have become an interesting research topic for future technologies. In this chapter, a tunneling field-effect transistor (TFET) that works on the principle of band-to-band tunneling (BTBT) is introduced. TFETs have potential to reduce the power consumption of the Integrated circuits (ICs). Scaling of supply voltage reduces the required switching energy; however, the fundamental limit of the subthreshold slope (SS)=60 mV/dec is a major obstacle in scaling of the supply voltage. TFETs overwhelm this SS limit and allow the scaling of the supply voltage. Although TFETs reduce the power dissipation of the device, the circuit design has remained a challenge due to its ambipolar characteristics, low ON current (ION), and asymmetric current flow through the device. Techniques to improve the ambipolar current, ION, and circuit design methodology with asymmetric devices are discussed in this chapter. Heterojunction and III–V semiconductors are the two major techniques that allow a band gap engineering to improve the performance of the TFETs. Therefore, a brief discussion of the III–V semiconductor-based TFETs and their circuit design parameters are also covered in this chapter.

Keywords

Tunneling field-effect transistor; band-to-band tunneling; steep subthreshold slope devices; High-k dielectric; area scaled tunnel FETs

Acknowledgment

Part of the work presented in this chapter is supported by the INSPIRE program of Department of Science and Technology, Government of India.

1.1 CMOS Power Trends

The idea of scaling the transistors dimension has resulted in a faster and increased integration density of a chip. However, high-density chips are suffering with high-power dissipation. Therefore, there is a need to reduce the power dissipation. The power consumption of the devices is increasing with the subsequent technology nodes (Fig. 1.1) [2]. There are two kinds of power dissipations in complementary metal oxide semiconductor (CMOS) circuit design: static power dissipation and dynamic power dissipation. Typically, the dynamic power consumption is higher than the static power dissipation. Nevertheless, the situation changes with scaling down of the metal oxide semiconductor field-effect transistor (MOSFET) size. It means, the static power increases with every new technology nodes. The increase in the static power with scaling of the gate length of the device is depicted in Fig. 1.1. It indicates that the leakage power dissipation has been growing with scaling of the technology node and exceeds the dynamic power dissipation below 65 nm technology node.

Figure 1.1 Power dissipation trend based on international technology roadmap for semiconductors [1].

To maintain the power performance and a high speed of the device, the power supply as well as the threshold voltage must be scale down in proportion to the channel length. However, a decrease in threshold voltage increases the OFF current (IOFF) that increases the static power dissipation of the device up to an unacceptable level. Therefore, scaling of threshold voltage of the MOSFET device is limited by the fundamental minimum SS of 60 mV/dec [3]. Fig. 1.2 indicates that it is not possible to scale down the threshold voltage in proportion to supply voltage that reduces the overdrive voltage. Consequently, scaling of the supply voltage out-of-proportion to the threshold voltage reduces the drive current of device that results in a slower speed. Therefore, there are two major consequences of the nonscalability of the threshold voltage of MOSFETs:

1. Supply voltage scaling slowed down due to the reduction in overdrive voltage (Table 1.1).

2. Scaling of transistor dimensions without scaling the supply voltage increases the electric field inside the channel that enhances the leakage current.

Table 1.1

Figure 1.2 Supply voltage and threshold voltage scaling trends based on international technology roadmap for semiconductors [1].

To overcome these problems, steep slope transistors attracted attention of device community researchers. A number of steep slope devices like impact ionization field-effect transistors (FETs), piezoelectric transistors, electromechanical FETs, feedback FETs, ferroelectric FETs, and tunneling field-effect transistors (TFETs) have been investigated. However, TFETs are the most promising device due to their MOSFET like device structures. TFETs work on the principle of band-to-band tunneling (BTBT) that is a quantum mechanical phenomenon. A brief description of quantum mechanical tunneling is presented in the next section.

1.2 Tunneling Phenomena

Tunneling of charge carriers through a potential barrier is a quantum mechanical phenomenon that occurs due to wave nature of the charge particle at small dimensions. Incidence of charge particle on a potential barrier of height more than the energy of the charge particle, it reflects or tunnel through it. The tunneling probability of the charge carrier depends on the potential barrier height, width, shape, and tunneling mass of the charge carrier [4]. The wave vector of the charge carrier is real in the incident and transmitted regions, but imaginary in the tunneling region. The imaginary wave vector in the tunneling region causes an exponential decay of the wave function amplitude and reduces the probability of transmission (Fig. 1.3). The tunneling of charge carriers is well understood in areas like tunneling of the electron across gate oxide, tunnel diodes, etc. This section focuses on the BTBT mechanism that describes the tunneling of the electrons from the valence band to the conduction band of a semiconductor.

Figure 1.3 Tunneling through a rectangular potential barrier.

The rate of BTBT across a potential barrier can be calculated using Kane’s approach and Wentzel–Kramers–Brillouin (WKB) approach. Although, WKB approach is different from Kane’s approach, it provides a similar result on simplification.

1.2.1 Kane’s Formulation

Kane formulated the band-to-band generation rate (cm−3 s−1) for the Zener tunneling from the valence band to the conduction band in a semiconductor [5]. The basic approach was based on the concept of the time-dependent perturbation theory, and Fermi’s Golden rule to calculate the generation rate in the conduction band of semiconductors.

(1.1)

is the sum of the Bloch states in the conduction band of the semiconductor, and H is the perturbation operator. Eq. (1.1) yields the expression of BTBT generation as follows:

(1.2)

where q is unit electron charge, m* is effective mass of the electron, Eg is effective energy band gap of the semiconductor, and E is electric field across the tunneling region. Eq. (1.2) indicates that the BTBT generation rate exponentially depends on the electric field.

1.2.2 WKB Approximation

The WKB approximation allows an alternative approach to calculate the BTBT generation rate. In this approach, a sum of all valence states with the momentum directed toward the tunneling barrier is considered for tunneling probability calculation. During the tunneling process, the energy and momentum of the charge carriers remain conserved. In one dimension, the tunneling probability can be expressed by the WKB approximation as [6]

(1.3)

where d is the tunneling barrier width, and k(x) is the wave vector of the charge carrier. The wave vector k(x) can be expressed as

(1.4)

where E is the energy of the charge carrier, m* is the effective mass of the electron, and V is the potential profile that can be given by the shape of the potential barrier.

1.3 Tunneling Field-Effect Transistors

The BTBT tunneling mechanism across a reverse biased junction realizes the steep slope current–voltage (I–V) characteristics. TFETs utilize this property of the reverse bias junction; it means current conduction in TFETs is based on the BTBT mechanism that improves SS. This makes TFETs a low-power device. Moreover, the process flow of TFETs is similar to MOSFETs and hence it can make the use of existing Si CMOS design and manufacturing infrastructure. This provides an opportunity to improve the integration density and performance of TFET-based integrated circuits (ICs). Furthermore, the structure of the TFET is similar to the MOSFET structure except the doping of source and drain is of opposite kind in TFETs. The schematic of an nTFET cross section and its band diagram in ON and OFF state is portrayed in Fig. 1.4. It consists of a highly doped p-type source, an intrinsic channel, and an n-type drain region [6].

Figure 1.4 (A) Schematic of a nTFET cross section. (B) Band diagram of nTFET along the channel in ON and OFF states.

A positive voltage at the drain terminal reverse biases the source–channel and drain–channel junctions. In the absence of gate voltage (VGS), due to potential barrier neither thermionic nor band to band tunneling current flows. Therefore, the IOFF of TFETs is very small that makes it an energy efficient device. In ON state, application of positive VGS pushes the conduction band down in the channel region (Fig. 1.4B). It creates a tunneling path between source band and channel conduction bands. Therefore, TFETs operate on the principle of BTBT generation instead of the thermionic emission. Since the current flow in the TFETs is contributed by the valence band electrons of the source that contains lower energy, the TFETs are thermally cooled system and the SS of TFETs are not expected to be limited by the temperature [3].

1.3.1 Current–Voltage Characteristics

In the earlier sections, the steep slope property, device structure, and device physics of TFETs have been discussed. In this section, the I–V characteristics of the TFETs are described along with the physics. The I–V characteristics of a double gate TFET are depicted in Fig. 1.5. The transfer characteristics show a sub-60 SS. The value of drain current (IDS) is much smaller than the expected to compete with the CMOS technology.

Figure 1.5 (A) Transfer characteristics of TFET. (B) Output characteristics of TFET.

The application of positive VGS pulls down the channel band profile that increases the charge carrier concentration in the channel region. Initially, no BTBT take place across the source–channel junction and the IDS remains very small. However, as the VGS pulls down the channel conduction band below the source valence band (Fig. 1.4B), BTBT starts across the source–channel junction and a sharp increase in IDS is observed (Fig. 1.5B). Any further increase in VGS continues pulling down the channel conduction band, until it aligns with the drain conduction band. After that, the channel conduction band does not show any significant shift with a further increase in VGS, because the free charge carriers screen the effect of VGS on the surface potential of the channel. Therefore, initially, the IDS increases with VGS sharply and then the effect of VGS, on IDS, reduces (see Fig. 1.5A) [7]. As a result, the SS of TFETs increases with VGS.

An increase in the TFET drain voltage (VDS) reduces the number of the free charge carriers in the channel. Consequently, it increases the channel potential profile and hence the electric field across the source/channel junction, at the same VGS. Therefore, for small drain voltages, VDS and VGS both determine the tunnel junction status and hence IDS increases with the VDS. As the channel region becomes fully depleted, a further increase in VDS does not make any change on surface potential and hence IDS saturates. The saturation current in TFETs is determined by both VDS and VGS. Saturation current is high for higher VGS [7].

1.3.2 Capacitance–Voltage Characteristics

This section discuss about the gate capacitance components in TFETs. The ION and switching speeds in ICs depend on the capacitances. An understanding of the gate capacitance components is important for TFET-based circuit design. Fig. 1.6 depicts the components of gate capacitance in TFETs and its capacitance–voltage characteristics [8]. Current conduction in TFETs is due to the BTBT mechanism across the source–channel junction. In OFF state (VGS=0 V, VDS=VDS,1), the tunneling probability is very low due to a wide depletion region at the source side junction that reduces the IOFF. In ON state (VGS=1 V, VDS=VDS,1), the tunneling barrier thickness becomes small that allow the charge carriers to tunnel across the source–channel junction. Since the current conduction in TFETs is by the BTBT mechanism, the ION of TFETs is very low as compared to the MOSFETs. Therefore, in ON state (VGS=VDS=1 V), a lower ION leads to reduced gate-to-source capacitance (Cgs) of TFETs [8]. Moreover, there is a very small potential drop at the drain–channel junction of TFETs as compared to the large reverse bias in MOSFETs (see Fig. 1.6B). This causes a comparatively larger gate-to-drain capacitance (Cgd) in TFETs [9]. It is interesting to note that the total gate capacitance Cgg is entirely dominated by the Cgd in TFETs in contrast to MOSFETs, where both Cgs and Cgd contribute significantly.

Figure 1.6 (A) Components of gate capacitances in TFETs. (B) Capacitance–voltage characteristics of TFETs, showing gate capacitance and its components as a function of the VGS.

1.4 Challenges for TFETs

To outperform the CMOS technology, TFETs need to achieve the highION (in the range of hundreds of mA), the lowest possible SS (<60 mV/dec), lowIOFF, and supply voltage less than 0.5 V, simultaneously. However, TFETs are facing the problem of the lower ION due to BTBT mechanism of current conduction. A number of techniques have been proposed to improve the ION of the TFETs including different device structures as well as material systems. Other challenges for TFETs include its ambipolar behavior and high Millar capacitance.

1.4.1 ON Current Performance Boosters

As discussed earlier the ION of the TFETs is low due to BTBT current conduction mechanism. However, it can be improved in a number of ways like area scaled TFET design techniques, use of high-k dielectric gate oxides, using III–V semiconductors, and using the heterojunction-based TFET (HTFET) structures. Some important techniques to enhance ION is presented as follows.

1.4.1.1 High-k gate dielectric

The capacitance coupling between the gate and tunnel junction can be determined by the gate dielectric. High-k gate dielectric leads a better control of the gate on TFETs that improves the SS as well as ION of the device. The thickness of the gate dielectric affects the ION of the device with scaling of the gate oxide thickness results in an increase in ION [10]. In addition to improvement in ION, the scaling of gate oxide leads better control of the gate on turning OFF the device [10]. However, the scaling of the gate oxide thickness can increase the gate leakage current. Another drawback of high-k gate dielectric is that it can also create the defects at the high-k dielectric/semiconductor interface, if high-k gate dielectric is directly deposited on the semiconductor. These defects can degrade the SS of the device and can lead to trap assisted tunneling that shows a higher temperature dependence of the SS. To reduce the interface defects, an interfacial layer with better oxide/semiconductor interface is required between high-k dielectric and semiconductor. For example, Al2O3/HfO2 bilayer gate oxide in InGaAs TFETs improves the SS in comparison to single HfO2 gate oxide.

1.4.1.2 Area scaled devices

In conventional TFETs, the tunneling occurs within 1–2 nm of the inversion layer. The basic problem is that the tunneling area cannot be increased by changing the technology or process parameter. Therefore, a new class of TFETs, called as area scaled TFETs, have been proposed that resolve the problem of low ION by allowing a wider tunneling area [11,12]. Fig. 1.7 presents the area scaled device structure. In area scaled devices, the improvement in ION is due to an increase in the tunneling cross section area of the device.

Figure 1.7 (A) A conventional TFET structure. (B) Area scaled TFET structure.

The current conduction in an area scaled TFET is by the vertical/line tunneling mechanism. In line tunneling, tunneling occurs in a direction parallel to the line of the electric force. In conventional TFETs the current conduction is due to the point tunneling (tunneling in a direction perpendicular to the line of electric force) mechanism. In addition to improvement in ION, an area scaled TFET also leads to an improvement in the SS due to a sharp increase in ION.

1.4.1.3 III–V HTFETs

The ION of TFETs can also be improved by material system engineering. Si is an indirect band semiconductor that has a band gap of 1.12 eV. The indirect tunneling mechanism and a larger potential barrier height of Si material reduce the tunneling probability and hence ION in Si-based TFETs. Therefore, direct band gap materials like III–V semiconductors can improve the tunneling probability at the source–channel junctions. III–V semiconductors offer a wide range of materials for band gap engineering. A small band gap material can increase the ION, but it also increases the IOFF that degrades the SS and ambipolar behavior of the device. These problems can be addressed by the application of heterojunction in TFETs. Heterojunction allows the band gap engineering in TFETs by using a combination of low band gap and high band gap materials. The use of a low band gap source material enhances the ION while the high band gap material in the channel and the drain region reduces the IOFF and ambipolar current.

For example, GaSb/InAs HTFET shows a better ION in comparison to InAs and GaSb homojunction transistors [13]. One possible way to further increase the ION of HTFET without degrading its SS is to make the use of ternary alloys. This idea is based on the fact that in Al x Ga (1−x) Sb, the valance band edge varies linearly with change in the molar fraction, without much significant change in lattice constant [14]. Hence, the molar fraction grading of Al x Ga (1−x) Sb can be used in the source region to minimize the source depletion region thickness [15]. The main problem of the molar-fraction-based device is the practical realization of the steep molar fraction grading. Therefore, there is a need of an alternate technique to increase ION of GaSb/InAs HTFETs. Another method to increase the ION without degrading the SS is the formation of GaSb quantum well in the InAs source region [16]. The operating principle of using the GaSb quantum well in InAs source is to create a significant hole density of state (DOS) at the source edge adjacent to the channel region. This enhancement in DOS helps in transmission of electron wave function in the channel region, and hence, increases the ION.

An In0.53Ga0.47As/InP heterojunction is also a very interesting material system for TFET application. The motivation behind In0.53Ga0.47As/InP HTFET is that the In0.53Ga0.47As with a narrow energy band gap (0.73 eV) at source side increases the BTBT probability and hence ION. Moreover, InP with a wide band gap (1.35 eV) in the drain side of the channel reduces the ambipolar and IOFF in the TFETs [17]. Another motivation toward this material system lies in the fact that InP is a material widely used in optical systems; application of InP in TFET can converge the electronics and photonics on a single platform. To further improve the ION without degrading the SS and ambipolar characteristics, In0.53Ga0.47As/In0.53Ga0.47As/InP/InP material system can be used. In this material system further insertion of In0.53Ga0.47As at the source side channel reduces the tunneling path, and hence, enhances the ION.

Although the heterojunctions improve the performance of the TFETs, two types of heterojunctions are of specific importance: the staggered gap and the broken gap (Fig. 1.8). Under bias conditions, the staggered gap heterojunctions provide a reduced tunneling length as compared to homojunctions that leads to a better performance of HTFETs. For the broken-gap-type heterojunctions, there is no potential barrier region to pass through that offers a high transmission probability. However, the IOFF in broken gap HTFETs is comparatively high due to the absence of a significant potential barrier region.

Figure 1.8 (A) Staggered band alignment heterojunction. (B) Broken band alignment heterojunction.

The drawback of III–V semiconductors is its lower DOS that reduces the tunneling probability and hence ION of the device. Another drawback of III–V semiconductor is the difference in DOS of the conduction band and valence band [18]. This causes a difference in performance of pTFETs and nTFETs that creates a problem for complementary digital logic design. The low DOS of the conduction band in III–V semiconductor results in a large source doping degeneracy for pTFET. Heavily doping the semiconductor to increase ION exposes the exponential tail of Fermi–Dirac distribution that increases the SS value of TFET. Therefore, the optimum doping of pTFET is lower than nTFET. This difference in pTFET and nTFET causes problem in complementary implementation of TFET circuits. The n–n+–p+–i–pTFET structure can block the injection of a hot carrier from the source to channel by maintaining a high electric field at tunnel junction [19]. However, light doping n-region of the source can result in an increase in series resistance at the source side. An HTFET can also improve the performance of pTFETs, since hetero source material has a large conduction band DOS like silicon.

1.4.2 Ambipolarity

Symmetric TFETs shows ambipolar device characteristic [20]. It demonstrates n-type behavior with the electron as a dominant charge carrier for positive VGS, and p-type behavior with hole as a dominant charge carrier for negative VGS. For p-type behavior, the n-type drain works as a source region and p-type source behaves as a drain region (Fig. 1.9). As a result, in OFF state, the band diagram of a pTFET is similar to nTFET that suppress the BTBT and results in a small value of IOFF. Application of negative VGS uplifts the band in the channel region (Fig. 1.9). A BTBT starts as soon as the channel valence band (EV) is lifted up to the conduction band (EC) of the n-type drain region. This results in BTBT of the channel valence band electron in the drain conduction band region. As a result. there is current conduction in symmetric TFETs for both positive and negative VGS. The ambipolarity of the TFETs is a major drawback in complimentary digital logic design using TFETs [20]. To overcome the problem of the ambipolarity, different device structure and device design technique have been proposed.

Figure 1.9 Band diagram of TFETs in ON, OFF, and ambipolar states.

One method to reduce the ambipolar behavior of TFETs is asymmetric source–drain doping concentration. In this method, the doping concentration of the drain is kept lower than the source doping concentration that widens the barrier thickness at the drain–channel junction. It reduces the BTBT at the drain–channel junction for negative VGS, as the BTBT reduces exponentially with an increase in tunneling barrier width. On the other hand, the ION remains unchanged due to a reduction in drain doping concentration, as it is controlled by the electron tunneling at the source–channel junction.

Other techniques to reduce the ambipolar current are gate–drain underlap structure [21], gate–drain overlap structure [22], hetero-gate-dielectric-based TFETs [23], etc. The ION of the TFETs depends on the source doping concentration and electron concentration of the channel near the source region. Therefore, it is possible to design a TFET with a resistance in the channel region near the drain without affecting the ION of device. The high resistance region near the drain can be created by the gate–drain underlap structure that can suppress the ambipolar current effectively. The gate–drain underlap structure reduces the impact of the gate on drain–channel junction and hence reduces ambipolar current. Similarly, in gate–drain overlap structure, application of negative VGS depletes the n-type drain region near drain–channel junction that reduces the band bending at the junction for negative VGS reducing the ambipolar current.

1.5 TFET Characteristics and Impact on the Circuit Design

In this section the challenges and advantages of TFETs from circuit design prospective has been discussed. On one hand, the TFET properties like a lower SS, lower threshold voltage, and low supply voltage operation provide an opportunity for low-power TFET-based circuit design. On the other hand, unidirectional conduction, delayed saturation, and a higher value of Cgd are the major challenges for TFET-based circuit designs. Therefore, the impact of properties of TFETs, like unidirectional conduction, delayed saturation, and higher Miller capacitances, on functionality of the circuits has been described.

1.5.1 Unidirectional Conduction

Unlike MOSFETs, the doping in the source and drain of TFETs is of the opposite kind that makes it operate as a reverse biased gated p–i–n diode. This causes unidirectional current conduction characteristics of TFETs, in contrast to symmetric source–drain MOSFETs. Consequently, the device source–drain orientation needs to be addressed in TFET-based circuit design that creates complexity. The design of the pass transistor logic using a single transistor is not possible as it requires bidirectional conduction. Therefore, additional transistors are required to design pass transistor logic using TFETs. However, in some circuits (e.g., TFET radio frequency (RF) rectifiers) the unidirectional current conduction simultaneously improves the reverse leakage current and the power loss