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ASIC and FPGA Verification: A Guide to Component Modeling
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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
Related to ASIC and FPGA Verification
Titles in the series (21)
ASIC and FPGA Verification: A Guide to Component Modeling Rating: 5 out of 5 stars5/5Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Rating: 0 out of 5 stars0 ratingsEmbedded DSP Processor Design: Application Specific Instruction Set Processors Rating: 0 out of 5 stars0 ratingsProcessor Description Languages Rating: 5 out of 5 stars5/5Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores Rating: 5 out of 5 stars5/5System Level Design with Rosetta Rating: 0 out of 5 stars0 ratingsReadings in Hardware/Software Co-Design Rating: 3 out of 5 stars3/5The Designer's Guide to VHDL Rating: 4 out of 5 stars4/5The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling Rating: 5 out of 5 stars5/5Verification Techniques for System-Level Design Rating: 0 out of 5 stars0 ratingsModeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation Rating: 0 out of 5 stars0 ratingsESL Design and Verification: A Prescription for Electronic System Level Methodology Rating: 0 out of 5 stars0 ratingsMultiprocessor Systems-on-Chips Rating: 0 out of 5 stars0 ratingsAspect-Oriented Programming with the e Verification Language: A Pragmatic Guide for Testbench Developers Rating: 0 out of 5 stars0 ratingsSystem-on-Chip Test Architectures: Nanometer Design for Testability Rating: 0 out of 5 stars0 ratingsVHDL-2008: Just the New Stuff Rating: 5 out of 5 stars5/5On-Chip Communication Architectures: System on Chip Interconnect Rating: 0 out of 5 stars0 ratingsNetworks on Chips: Technology and Tools Rating: 5 out of 5 stars5/5Network Processors: Architecture, Programming, and Implementation Rating: 0 out of 5 stars0 ratingsElectronic Design Automation: Synthesis, Verification, and Test Rating: 0 out of 5 stars0 ratingsLow-Power Design of Nanometer FPGAs: Architecture and EDA Rating: 0 out of 5 stars0 ratings
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ASIC and FPGA Verification - Richard Munden
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