Sustainable Wireless Network-on-Chip Architectures

By Jacob Murray, Paul Wettin, Partha Pratim Pande and Behrooz Shirazi

Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern.

The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots.

• Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy
• Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques
• Describes joint strategies for network- and core-level sustainability
• Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures

• Language: English
• Publisher: Elsevier Science
• Release date: Mar 25, 2016
• ISBN: 9780128036518

Jacob Murray

Jacob A. Murray received his PhD in Electrical and Computer Engineering at the School of Electrical Engineering and Computer Science, Washington State University in 2014 and received his BS in Computer Engineering at Washington State University in 2010. He is a Clinical Assistant Professor and Program Coordinator at the School of Electrical Engineering and Computer Science, Washington State University, Everett. His current research interests include sustainable and low-power design for on-chip interconnection networks, routing for wireless on-chip communication networks, and temperature-aware design for topology-agnostic networks. He has been a Harold Frank Entrepreneur and participated as one of five undergraduate finalist teams in the 2010 National Collegiate Inventors Competition. He is a member of Tau Beta Pi, the national engineering honors society, and a member of the IEEE.

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Chapter 1

Introduction

Abstract

Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip, namely, those that incorporate modularity and explicit parallelism. Researchers have recently pursued scalable communication-centric interconnect fabrics, such as Networks-on-Chip (NoCs), which possess many features that are particularly attractive. These communication-centric interconnect fabrics are characterized by varying trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. This chapter focuses on traditional NoC topologies, routing strategies, and interconnect backbone.

Keywords

Network-on-chip; multicore; interconnect topologies; hop count; routing

The Network-on-Chip Paradigm

Massive multicore processors are enablers for numerous information and communication technology innovations spanning various domains, including healthcare, defense, entertainment, etc. Continuing progress and integration levels in silicon technologies make possible complete, end-user systems on a single chip in order to meet the growing needs for computation-intensive applications. Clock scaling to meet these needs is not feasible as power and heat become dominant constraints to chip design. As current VLSI technologies can integrate many transistors, parallelism is the key to keeping up with the computational demands. However, the number of cores needed to keep up with the computational demands is drastically increasing.

Chips with ever-increasing cores have been demonstrated by industry. Some examples include Intel’s TeraScale processor research program (Held et al., 2006), having developed an 80-core research processor and a 48-core single-chip cloud computer (Vangal et al., 2008; Howard et al., 2010). An Intel 22 nm, 256-core chip has also recently been developed (Chen et al., 2014). Tilera has developed a line of TILE-Gx and TILE-Mx processors with core counts up to 100. As designs with 100s of embedded cores are developed, a need for a platform-based interconnection infrastructure has arisen. As such, the Network-on-Chip (NoC) paradigm has been introduced to provide modularity and regularity via a dedicated infrastructure for interconnections. NoCs have been used in the abovementioned processors and additionally, this paradigm has introduced a new area for research into the many-core architecture domain.

Traditional NoC Interconnect Topologies

Traditionally, few cores integrated on a single chip allow for simple bus interconnect strategies, where one sender broadcasts data onto the bus, and the intended receiver reads the bus line. As the number of cores scales, the bus quickly becomes a bottleneck as more cores are trying to communicate on the bus. While this consists of minimal overhead, network congestion leads to high latency and low throughput. Latency is defined as the amount of time that passes when the sending core sends out data to the point in which the receiving core obtains that data. Throughput is defined as the total amount of data moving at any one given instant of time within the NoC. An example of a 16-core bus network can be seen in Fig. 1.1a. Direct extensions of the bus network include multibus and hierarchical-bus networks (Thepayasuwan et al., 2004). Multiple busses can be added into the network so a single core is not able to congest the entire network, allowing additional cores to be able to transfer their data as well.

Figure 1.1 Various 16-core traditional NoC interconnect topologies: (a) Bus, (b) ring, (c) star-ring, (d) mesh, (e) torus, (f) folded torus, (g) binary tree, (h) quad tree, and (i) butterfly fat tree.

A continuation of the bus network is the ring and star-ring networks, seen in Fig. 1.1b and c, respectively. For a ring, each core is connected to its own individual network switch and the network switches are connected to two neighbors. In the case of the star-ring an additional central network switch connects to all other switches. The dedicated switch in the star-ring network allows the core to send its data and do other tasks while the network switches take care of data delivery. An insufficiency with the ring network is that the average hop count between cores is relatively high as can be seen in Table 1.1. Hop count is the number of links that data has to traverse before arriving at the destination core from the sending core considering uniform random traffic. The more cores that are inserted into the ring network, on average, the more number of hops it takes to reach any other core. The star-ring network was created to introduce shortcuts into the network to try and reduce the average hop count within the network, reducing the average hop count from 6.2 to 3.8 for a 16-core network, as seen in Table 1.1. However, this requires a very large network switch, with N ports, for an N core network to be built that has to connect to each of the other network switches. Although the central switch reduces the average hop count, it also creates a traffic bottleneck; all of the traffic will try to use this network switch as it creates shortcuts in the network.

Table 1.1

Scalability of Various Traditional NoC Interconnect Topologies

Increasing the average number of links per switch can decrease the average hop count of the network. The mesh network produces a regular grid-like structure where each network switch is connected to each of its cardinal neighbors. The average number of links per switch is greater in mesh than that of a ring network, 3:2 for a 16-core network, which can be seen in Table 1.1. A 16-core mesh can be seen in Fig. 1.1d. The mesh layout has been implemented in existing chips and works well as it is easy to construct and scale using a standard processing tile (which includes a processor, cache, and an NoC switch). While it has relatively good throughput, as it is scaled, paths begin to have large number of hops. In a simple example, communicating from one corner of the mesh to another takes (M−1)+(N−1) hops, where M and N are the number of rows and columns in the mesh, respectively. This growth in hop count can be seen in Table 1.1.

Another two topologies that are variations of mesh are the torus and folded torus as can be seen in Fig. 1.1e and f, respectively. In a torus, each switch is not only connected to its cardinal neighbors but also has extra links for each row and column that connects the first and last switch in each row and column, respectively. The folded torus is similar to the torus except that every other switch in a row or column is connected to each other, instead of its direct neighbors. This allows the connections between switches to be uniform in length for the folded torus instead of having a few connections that are physically long like that in a normal torus. Both the torus and folded torus topologies are easy to construct, just like the mesh network. These two networks can be designed using a standard processing tile, but have half the maximum hop count. The reduction in hop count is due to the connections that wrap around in torus, and the connections that can go the length of two hops, compared to a normal mesh, in the folded torus. This can be seen in Table