Emerging Nanoelectronic Devices

Emerging Nanoelectronic Devices focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future.  This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh perspective on emerging research devices in 26 up to date chapters written by the leading researchers in their respective areas. It supplements and extends the work performed by the Emerging Research Devices working group of the International Technology Roadmap for Semiconductors (ITRS). 

Key features: 

• Serves as an authoritative tutorial on innovative devices and architectures that populate the dynamic world of “Beyond CMOS” technologies.
• Provides a realistic assessment of the strengths, weaknesses and key unknowns associated with each technology.
• Suggests guidelines for the directions of future development of each technology.
• Emphasizes physical concepts over mathematical development.
• Provides an essential resource for students, researchers and practicing engineers.

• Language: English
• Publisher: Wiley
• Release date: Nov 26, 2014
• ISBN: 9781118958278

Book preview

Preface

Continued dimensional and functional1 scaling of CMOS2 integrated circuit technology is driving information processing3 systems into a broadening spectrum of new applications. Many of these applications are enabled by performance gains and/or increased complexity realized by scaling. Because dimensional scaling of CMOS eventually will approach fundamental limits, several new alternative information processing devices and microarchitectures for existing or new functions are being explored to sustain the historical integrated circuit scaling cadence and reduction of cost/function in future decades. This is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions (a.k.a. More than Moore), and new paradigms for systems architecture.

This book is based on the ITRS Emerging Research Device (ERD) International Technical Work Group's efforts over more than ten years to survey, research, and assess many of these new devices. As such, it provides an ITRS perspective on emerging research nanodevice technologies and serves as a bridge between CMOS and the realm of nanoelectronics beyond the end of CMOS dimensional and equivalent functional scaling. (Material challenges related to emerging research devices are addressed in a complementary ITRS chapter entitled Emerging Research Materials.)

An overarching goal of the ERD is to identify, assess, and catalog viable new information processing devices and systems architectures for their long-range potential and technological maturity, and to identify the scientific/technological challenges gating their acceptance by the semiconductor industry as having acceptable risk for further development. The intent is to provide an objective, informative resource for the constituent nanoelectronics communities pursuing: (1) research, (2) tool development, (3) funding support, and (4) investment, each directed to developing a new information processing technology. These communities include universities, research institutes, industrial research laboratories, tool suppliers, research funding agencies, and the semiconductor industry.

This goal is accomplished by addressing two technology-defining domains: (1) extending the functionality of the CMOS platform via heterogeneous integration of new technologies, and (2) stimulating the invention of a new information processing paradigm. The relationship between these domains is schematically illustrated in Figure P.1. The expansion of the CMOS platform by conventional dimensional and functional scaling is often called More Moore. The CMOS platform can be further extended by the More than Moore approach which is a relatively new subject. On the other hand, new information processing devices and architectures are often called Beyond CMOS technologies and are the main subjects addressed in this book. The heterogeneous integration of Beyond CMOS and More than Moore onto the More Moore platform will extend CMOS functionality to form the ultimate Extended CMOS.

Figure P.1 Relationship between More Moore, More than Moore, and Beyond CMOS (Source: ERD, Japan)

The book is partitioned into five sections: (1) Introduction, including a fundamental description of the physics of some nanodevices, (2) nanoelectronic memory devices, (3) nanoelectronic logic information processing devices, (4) concepts for emerging architectures, and (5) summary, conclusions, and outlook for nanoelectronic devices. Some detail is provided for each entry regarding operation principles, advantages, technical challenges, maturity, and its current and projected performance. Also included is a device and architectural focus combining emerging research devices offering specialized, unique functions as heterogeneous core processors integrated with a CMOS platform technology. This represents the nearer-term focus of this work, with the longer-term focus remaining on the discovery of an alternate information processing technology to supplement and to eventually replace digital CMOS.

Notes

1. Functional Scaling: Suppose that a system has been realized to execute a specific function in a given, currently available, technology. We say that system has been functionally scaled if the system is realized in an alternate technology such that it performs the identical function as the original system and offers improvements in at least one of size, power, speed, or cost, and does not degrade in any of the other metrics.

2. Martin Hilbert and Priscila López, 2001, The World's Technological Capacity to Store, Communicate, and Compute Information, Science, 332(6025), 60–65.

3. Information processing refers to the input, transmission, storage, manipulation or processing, and output of data. The scope of this book is restricted to data or information manipulation, transmission, and storage.

List of Contributors

Ethan C. Ahn, Department of Electrical Engineering, Stanford University, USA

Masakazu Aono, WPI Center for Materials Nanoarchitectonics, National Institute for Materials Science, Japan

Tetsuya Asai, Graduate School of Information Science and Technology, Hokkaido University, Japan

Behtash Behin-Aein, GLOBALFOUNDRIES Inc., USA

Benjamin F. Bory, Eindhoven University of Technology, The Netherlands

George Bourianoff, Components Research Group, Intel Corporation, USA

Geoffrey W. Burr, IBM, USA

An Chen, GLOBALFOUNDRIES Inc., USA

Donald M. Chiarulli, Department of Electrical and Computer Engineering, University of Pittsburgh, USA

György Csaba, University of Notre Dame, USA

Shamik Das, Nanosystems Group, The MITRE Corporation, USA

Denver H. Dash, Intel Science and Technology Center, USA

Supriyo Datta, Purdue University, USA

Vinh Quang Diep, Purdue University, USA

S. Burc Eryilmaz, Department of Electrical Engineering, Stanford University, USA

Yan Fang, Department of Electrical and Computer Engineering, University of Pittsburgh, USA

Scott Fong, Department of Electrical Engineering, Stanford University, USA

Aaron D. Franklin, Department of Electrical and Computer Engineering and Department of Chemistry, Duke University, USA

Paul Franzon, North Carolina State University, USA

Tsuyoshi Hasegawa, WPI Center for Materials Nanoarchitectonics, National Institute for Materials Science, Japan

Toshiro Hiramoto, Institute of Industrial Science, The University of Tokyo, Japan

James Hutchby, Semiconductor Research Corporation, USA

Louis Hutin, Department of Electrical Engineering and Computer Sciences, University of California, USA

Adrian M. Ionescu, Ecole Polytechnique Fédérale de Lausanne, Switzerland

Mahdi Jamali, University of Minnesota, USA

Rakesh Jeyasingh, Department of Electrical Engineering, Stanford University, USA

Alexander Khitun, Material Science and Engineering, University of California, USA

Angeline Klemm, University of Minnesota, USA

Takhee Lee, Department of Physics, Seoul National University, Korea

Steven P. Levitan, Department of Electrical and Computer Engineering, University of Pittsburgh, USA

Eike Linn, Institute of Electronic Materials II, RWTH Aachen University, Germany

Tsu-Jae King Liu, Department of Electrical Engineering and Computer Sciences, University of California, USA

Matthew J. Marinella, Sandia National Laboratories, USA

Hao Meng, Data Storage Institute, Singapore

Stephan Menzel, Peter Grünberg Institut (PGI-7), Forschungszentrum Jülich, Germany

Stefan C.J. Meskers, Eindhoven University of Technology, The Netherlands

Michael T. Niemier, University of Notre Dame, USA

Ferdinand Peper, Center for Information and Neural Networks, National Institute of Information and Communications Technology, USA

Wolfgang Porod, University of Notre Dame, USA

Mark A. Reed, Departments of Electrical Engineering and Applied Physics, Yale University, USA

Frank Schwierz, Technical University of Ilmenau, Germany

Hyunwook Song, Department of Applied Physics, Kyung Hee University, Korea

Narayan Srinivasa, Center for Neural and Emergent Systems, HRL Laboratories LLC, USA

Ken Takeuchi, Chuo University, Japan

Jian-Ping Wang, University of Minnesota, USA

Rainer Waser, Institute of Electronic Materials II, RWTH Aachen University, Germany; Peter Grünberg Institut (PGI-7), Forschungszentrum Jülich, Germany

H.-S. Philip Wong, Department of Electrical Engineering, Stanford University, USA

Victor V. Zhirnov, Semiconductor Research Corporation, USA

Acronyms

Part One

Introduction

1

The Nanoelectronics Roadmap

James Hutchby

Semiconductor Research Corporation, USA

1.1 Introduction

Over the past 40 years, the global impact of the computer or digital age on most individuals, cultures, and their economies, has been nothing less than breathtaking; it has shifted the communication and human interaction paradigm and has sparked creation of several major new industries. In short, electronics technology based on semiconductor devices and integrated circuits has changed how many of us live our lives and how we do our business.

For example, semiconductor device technology of the 1960s enabled development of large, centralized, power-consuming, main frame computers using discrete transistors to replace vacuum tube binary switches. The 1970s saw the advent of e-mail, desktop and portable calculators, the earliest Internet, digital watches, and the first applications of microprocessors. As complementary metal oxide semiconductor (CMOS) gates became the dominant low-power semiconductor technology in the 1980s, its explosion following Moore's Law1 [1] drove the development and broad application of personal and, later, laptop computers in the 1980s and 1990s. The world's capacity to process bits of information grew from 3.0 × 10⁸ MIPS in 1986, to 4.4 × 10⁹ MIPS in 1993, to 2.9 × 10¹¹ MIPS in 2000, and to 6.4 × 10¹² MIPS in 2007 [2].

Broadened commercial applications in the twenty-first century include Smart Phones, Global Positioning Satellite navigation systems, Digital Cameras, high definition flat panel TVs, tablet PCs, smart dining utensils (for managing food and caloric intake), and a variety of automotive sensor and information-processing electronics.

Much of the commercial success of the semiconductor industry has been driven by its ability to relentlessly follow Moore's Law in doubling the density of transistors every 2–3 years. This phenomenal technology scaling not only enabled new, more complex, applications and lowered the cost per transistor by 25–30%/year [3], it provided faster circuits with lower power dissipation. In this time period, the number of transistors on a chip increased from a few hundred/cm² to several billion/cm².

The value of the semiconductor and related electronics systems industries also can be judged by their impact on the United States and global economies. For example, the annual revenues of the semiconductor-based device industry exceeded US$ 300B in 2013, and the related electronics systems industry revenues were projected to exceed US$ 1.55 T in 2010 [4]. Also, from 1960 to 2007, the computer industry added only 0.3% of United States value, but it contributed 2.7% of economic growth and 25% of productivity gains [5].

As these examples illustrate, the rapid and ubiquitous penetration of information-processing technologies into new domains of application and their major economic impact combine to drive aggressive reduction of the size and cost of the basic information-processing element (i.e., the transistor or some new information processing element). However, as the size of the transistor continues to shrink, its structural composition is approaching a few hundred atoms and its operation is becoming prohibitively leaky thus enabling increased power dissipation. Eventually, the semiconductor industry will need a technology to supplement and extend CMOS beyond its fundamental scaling limit.

This raises the following questions: (1) how much further can the present CMOS-based electronics technology be scaled in size and cost; (2) what (if any) new physical mechanism and technology can either supplement, or eventually, replace CMOS as a medium for continued scaling of information-processing technology?

1.2 Technology Scaling: Impact and Issues

Scaling CMOS raises some additional important issues regarding increased power dissipation of aggressively scaled metal oxide semiconductor field effect transistors (MOSFETs) leading to unwieldy power density dissipated on a silicon CMOS chip. Historically, one could reduce the threshold voltage and, thereby, the source–drain voltage and power dissipation of a scaled MOSFET transistor in a CMOS gate. However, in recent years the allowable threshold voltage of a MOSFET has reached a minimum of 0.9–1.0 V. Consequently, as the transistor is further scaled its power dissipation increases. The power dissipation on a scaled chip has two sources. One source is the scaled transistors. The other source is the system of metal interconnects.

The physical operation of electronic devices ranging from the vacuum tube, to a variety of transistors and integrated circuits, has centered on the manipulation and storage of electronic charge. The next section discusses the limits of charge confinement and relates them to a fundamental scaling limit of CMOS.

1.3 Technology Scaling: Scaling Limits of Charge-based Devices

Operation of MOSFETs is based on manipulation of electronic charge transport from source to drain controlled by another charge placed on a gate [6]. Electrons placed on the source are prohibited (for the most part) from flowing spontaneously to the drain by an energy barrier formed by the gate/source and the source/drain potentials. Lowering this energy barrier by placing a positive charge on the gate allows electrons on the source to flow to the drain when assisted by a forward bias voltage. Conversely, these electrons on the drain are blocked from returning to the source by the drain/source energy barrier. The question then is: What is the minimum height (Eb) and width (a) of the gate/source potential energy barrier necessary to allow an electron to have equal probability of being either in the source or the drain?

Figure 1.1a illustrates manipulation of the energy barrier between the source and drain of a MOSFET by application of a voltage, Vgs, from the gate to the source, and another voltage, Vds, from the drain to the source. Altering these voltages changes the height and, to a lesser extent, the width of this energy barrier and, thereby, changes the confinement of electronic charge in either of two potential wells. One is defined by the source and the other by the drain. An idealized model of this source–gate–drain potential well structure is illustrated in Figure 1.1b.

Figure 1.1 Energy model for limiting device. (a) Cross-section of a MOSFET illustrating potential distributions and their effect on the potential barrier separating the source drain potential wells. (b) Idealized model of the potential barrier separating the source drain potential wells where: w = width of left-hand well (LHW) and right-hand well (RHW); a = barrier width; Eb = barrier energy

The model illustrated in Figure 1.2 is used to estimate the minimum width, amin, and height, Ebmin, needed to provide a 50% probability that a single electron is either in the source or drain potential well. Figure 1.2 also illustrates two processes for transmitting electrons either over the barrier by thermionic emission or through the barrier by quantum mechanical tunneling. Using these criteria, a limit value of a, amin = 1.5 nm and Ebmin = kTln2, where k is the Boltzmann constant, and T is absolute temperature in degrees Kelvin. An additional constraint requiring minimization of energy dissipated in changing potential wells sets amin = 5 nm.

Figure 1.2 Illustration of two processes for transmitting electrons either (a) over an energy barrier by thermionic emission, or (b) through the barrier by quantum mechanical tunneling

Since high-volume manufacturing technology for the 16 nm node is currently being ramped to full production, the 5 nm generation may go into manufacturing in 7 years or in 2020. The 8 nm generation may be in manufacturing as early as 2018. Consequently, scaling of CMOS-based information-processing technology will face fundamental limits within the next 5–7 years or by 2020. This determines a need to have any new technology for extending CMOS in place by that time. Furthermore, this analysis suggests that the search for a new information-processing technology and paradigm should consider a new token to replace the electronic charge or a new information-processing paradigm that does not depend on confinement of the electronic charge.

1.4 The International Technology Roadmap for Semiconductors

Formed in 1991 by the United States Semiconductor Industry Association (SIA) assisted by Semiconductor Research Corp. (SRC) and SEMATECH, the United States National Technology Roadmap for Semiconductors (NTRS) brought together scientists and technologists from the United States microelectronics manufacturing, supplier, and academic communities and tasked them to forecast technological scaling of MOSFET integrated circuits and all related technologies 15 years into the future. The first NTRS was published in 1992.

Recognizing the value of including international microelectronics communities, the International Roadmap Committee (IRC) established the International Technology Roadmap for Semiconductors (ITRS) in 19982. The ITRS was tasked to develop and maintain a 15 year assessment of the semiconductor industry's future technology requirements. These future needs drive present-day strategies for world-wide research and development among manufacturers' research facilities, universities, national laboratories, and tool manufacturers in 17 topical areas ranging from basic or emerging research materials and emerging research devices to design and systems drivers. This book is focused on Emerging Research Devices.

1.5 ITRS Emerging Research Devices International Technology Working Group

As the size of the transistor continues to shrink, its structural composition is approaching a few hundred atoms and its operation is becoming prohibitively leaky, thereby leading to increased power dissipation. Briefly mentioned above, the semiconductor industry eventually will need a technology to supplement and extend CMOS beyond its fundamental scaling limit and one day even to replace CMOS.

As this need took on some urgency, the ITRS International Roadmap Committee (the ITRS governance committee) formed a new technical work group; this group became the Emerging Research Devices (ERD) International Technology Working Group (ITWG).

1.5.1 ERD Editorial Team

The ERD International Technology Working Group (ERD ITWG) is a large international group of approximately 80 individuals who contribute in some way to the work of the ERD Team over a 2 year cycle to produce a new ERD chapter for each updated ITRS. The ERD Editorial Team consists of approximately 12 actively engaged individuals, 8 of whom represent eight companies, 2 represent two universities, and 2 represent one consortium. This Editorial Team provides leadership for the ERD ITWG. Many ERD active contributors manage research groups that address nanoelectronics topics within their organizations and a few members of ERD are actively engaged practicing researchers contributing to this field. Much of the text in the ERD chapter is written by practicing researchers well-recognized for their leadership in the field in which they make their contributions. Their contributions are then vetted by the ERD Editorial Team and the IRC to ensure balance and accuracy of any claims or projections made for a Technology Entry.

1.5.2 Vision and Mission

The vision of the ERD is to assist the nanoelectronics research community to invent and demonstrate feasibility of new technologies to extend information processing beyond the reach of Si technology and to be a resource to the Semiconductor Industry in their evaluation of these nanodevices.

The mission of the ERD ITWG is to offer substantive input to our reader communities related to the viability of proposed nanoelectronic devices to live up to their claimed potential in heir maturity. The targeted reader communities include the global research community (including industrial, university, and government laboratories), relevant government agencies, industry technology directors and managers, and the supplier communities. ERD evaluates significant new concepts for nanodevices proposed to supplement and/or replace the silicon MOSFET for information processing. This is accomplished by critically assessing the suitability and maturity of a nanodevice concept for sustaining information processing beyond that attainable with ultimately scaled CMOS thereby leading to promising new approach(es) to memory and logic technologies to be implemented by 2020–2026.

1.5.3 Scope

The scope of ERDs activities embraces evaluating emerging research memory (including solid state storage), logic, information processing, More-than-Moore, and new nanoarchitecture technologies enabled by promising new nanodevices together with the requisite materials and process technologies chosen to fabricate the device and test structures [in collaboration with the Emerging Research Materials (ERM) work group].

Evaluation of a candidate nanodevice includes assessing its scaling potential, power dissipation, speed, operation temperature, internal gain, technological, and/or architectural compatibility with CMOS. The primary question addressed by this evaluation process is: Assuming a device reaches its full maturity in fabrication and operation, how would it compare with ultimately scaled CMOS and to what extent can it be scaled further? Evaluation also includes identifying the most important scientific and technological questions and issues that must be resolved to advance acceptance of the device for further attention and accelerated development. The scope includes modeling and simulation and those metrologies required by the research community to establish and demonstrate the operation and feasibility of a new device.

Evaluation is further discussed in Section 1.6.1.

1.6 Guiding Performance Criteria

1.6.1 Nanoinformation Processing

First, we need a clear understanding of just what is meant by information. Webster's New International Dictionary defines information for broad popular use as the communication or reception of knowledge or intelligence. For focused digital computing and digital signal-processing applications, information is defined in its most restricted technical sense as a sequence of symbols that can be interpreted as a message. These symbols take on a specific meaning when they are encoded according to a particular algorithm. The questions addressed by the ERD work group in considering a proposed new technology include:

In a new technology, how can a single bit of information be physically represented – what is the operative information-bearing token?" (e.g., the electron in electronic circuits or the bead in an abacus.)

What property of the information token is used as the state variable to define and sense the state? (e.g., for an electron the commonly used state variable is charge and its presence/absence is sensed by a voltage across the drain load capacitance.3 For the abacus the state variable is the mass and physical position of a bead.)

How can the state variable be manipulated to reliably change the logic state? (e.g., in a CMOS gate the voltage of the load capacitor can be increased and decreased by placement and removal of electrons on to and off of the load capacitor. For the abacus it is the movement of a bead to and from a defined position.)

How can the state variable in one position communicate with a state variable in another position to perform a function? (e.g., in CMOS, copper metal interconnect wires conduct charge/voltage from one site another, and in an abacus, nimble fingers perform the task of moving a bead from one position to another.)

What is the performance claimed for the new technology in terms of its power dissipation, switching speed, and so on? How does this compare with the performance of ultimately scaled silicon?

What fabrication and manufacturing issues need to be addressed and resolved?

What fundamental and technology issues need to be addressed and resolved to demonstrate the promise and feasibility of the proposed technology?

1.6.2 Nanoelectronic Device Taxonomy

Information processing to accomplish a specific system function, in general, requires several different interactive layers of technology. The objective of this section is to carefully delineate a taxonomy of these layers to further distinguish the scope of this book from that of the Emerging Research Materials chapter and the Systems Design chapter in the ITRS. The scope of this book addresses the Device and the Data Representation layers shown in Figure 1.3.

One comprehensive top-down list of these layers begins with the required application or system function, leading to system architecture, micro- or nanoarchitecture, circuits, devices, and materials. As shown in Figure 1.3 a different bottom-up representation of this hierarchy begins with the lowest physical layer represented by a computational or information token (e.g., the electron) and ends with the highest layer represented by the architecture. In this more schematic representation, focused on generic information processing at the device/circuit level, a fundamental unit of information (e.g., a bit) is represented by the value of a property (e.g., presence or absence of electronic charge or the polarity of spin) of a computational information token, for example, the position of a bead in the ancient abacus calculator or the electronic charge or voltage state of a nodal capacitance in CMOS logic. A device provides the physical means of representing and manipulating a property (e.g., position of an electronic charge) of a computational information token among its two or more allowed discrete states. Eventually, device concepts may transition from simple binary switches to devices with more complex information processing functionality.

The device is a physical structure resulting from the assemblage of a variety of materials possessing certain desired properties obtained through exercising a set of fabrication processes. An important layer, therefore, encompasses the various materials and processes necessary to fabricate the required device structure, which is the domain of the ERM International Technical Work Group. The data representation layer is how the state variable property of the information token is encoded by the assemblage of devices to process the bits or data. Two of the most common examples of data representation are binary digital and continuous or analog signaling. In some cases, the data are represented as arrays or images which then become the fundamental datum of computation in either primitive or compressed form. This layer is within the scope of the ERD ITWG. The architecture plane encompasses three subclasses of this taxonomy: (1) the nanoarchitecture or physical arrangement or assemblage of devices to form higher level functional primitives to represent and enable execution of a computational model, (2) the computational model that describes the algorithm by which information is processed using the primitives, for example, logic, arithmetic, memory, cellular nonlinear network (CNN), and (3) the system-level architecture that describes the conceptual structure and functional behavior of the system exercising the computational model. Subclass (1) is within the scope of the ERD Technical Work Group, and subclasses (2) and (3) are within the scope of the Design Technical Work group. The elements shown in the red-lined yellow boxes (left side of Fig. 1.3) represent the current CMOS platform technology that is based on electronic charge as a binary information token. This state token serves as the foundation for the von Neumann computational system architecture. Analog data representation also is included in the current CMOS platform technology. The other entries grouped in these five categories summarize individual approaches that, combined in some yet to be determined highly innovative fashion, may provide a new highly scalable information-processing paradigm.

Figure 1.3 Taxonomy for nanoinformation processing devices

1.6.3 Fundamental Guiding Principles – Beyond CMOS Information Processing

In considering the many disparate new approaches proposed to provide order of magnitude scaling of information processing beyond that attainable with ultimately scaled CMOS, the ERD Editorial Team proposed the following comprehensive set of guiding principles. We believe these Guiding Principles provide a useful structure for directing research on any information-processing technology to dramatically enhance scaling of functional density and performance while simultaneously reducing the energy dissipated per functional operation. Further this new technology would need to be realizable using a highly manufacturable fabrication process.

1.6.3.1 Computational Information Variable(s) other than Solely Electron Charge

In seeking new device opportunities, it is important to understand not only the device characteristics, but also how connected systems of these devices might be used to perform complex logic functions [7]. The basic computational element in current digital information processing systems is the binary switch. In its most fundamental form, it consists of:

Two states 0 and 1 (state variables), which are equally attainable and distinguishable;

A means to control the change of the state (WRITE);

A means to read the state;

A means to communicate with other binary switches (TALK).

The system state representation controls (WRITE), and the READ and TALK operations are all represented by a physical property of entities such as particles, quasi-particles, collections of particles, and so on. These physical entities are called tokens. Each token has a set of physical attributes associated with it (e.g., charge, mass, spin) and it is the physical interaction between the token attributes within the device structure that determines the operation and the resulting state of the device. In most cases, an attribute can assume several values and for this reason, we also call them state variables.

The estimated performance comparison of devices utilizing an alternative token (e.g., an electron, position of an atom) with an alternative state variable (e.g., charge and voltage, spin, current) to ultimately scaled CMOS should be made as early in a program as possible to down-select and identify key trade-offs.

1.6.3.2 Nonthermal Equilibrium Systems

These are systems that are out of equilibrium with the ambient thermal environment for some period of their operation, thereby reducing the perturbations of stored information energy in the system caused by thermal interactions with the environment. The purpose is to allow lower energy computational processing while maintaining information integrity.

1.6.3.3 Novel Energy Transfer Interactions

These interactions could provide the interconnect function between communicating information processing elements. Energy transfer mechanisms for device interconnection could be based on short-range interactions including, for example, quantum exchange and double exchange interactions, electron hopping, Förster coupling (dipole–dipole coupling), tunneling and coherent phonons.

1.6.3.4 Nanoscale Thermal Management

This could be accomplished by manipulating lattice phonons for constructive energy transport and heat removal.

1.6.3.5 Sublithographic Manufacturing Process

One example of this principle is directed self-assembly of complex structures composed of nanoscale building blocks. These self-assembly approaches should address nonregular, hierarchically organized structures, be tied to specific device ideas, and be consistent with high-volume manufacturing processes.

1.6.3.6 Alternative Architectures

In this case, architecture is the functional arrangement on a single chip of interconnected devices that includes embedded computational components. These architectures could utilize, for special purposes, novel devices other than CMOS to perform unique functions.

1.6.4 Current Technology Requirements for CMOS Extension and Beyond CMOS Memory and Logic Technologies

Some emerging nanoscale devices discussed in this book are charge-based structures proposed to extend CMOS to the end of the current roadmap. Other emerging devices offer new computational information tokens and will likely require new fabrication technologies.

A set of relevance or evaluation criteria, defined below, are used to parameterize the extent to which proposed CMOS Extension and Beyond CMOS technologies are applicable to memory or information-processing applications. The relevance criteria are: (1) scalability, (2) speed, (3) energy efficiency, (4) gain (logic) or ON/OFF ratio (memory), (5) operational reliability, (6) operational temperature, (7) CMOS technological compatibility, and (8) CMOS architectural compatibility. Definitions of these evaluation criteria follow:

1. Scalability: First and foremost the major incentive for developing and investing in a new information-processing technology is to discover and exploit a new domain for scaling information-processing functional density and throughput per Joule substantially beyond that attainable by ultimately-scaled CMOS. Silicon-based CMOS has provided several decades of scaling of MOSFET densities. The goal of a new information-processing technology is to replicate this success by providing additional decades of functional and information throughput rate scaling using a new technology. In other words, it should be possible to articulate a Moore's Law for the proposed technology over additional decades.

2. Speed: A future information-processing technology must continue to provide (at least) incremental improvements in speed beyond that attainable by ultimately scaled CMOS technology. In addition, nanodevices that implement both logic and memory functions in the same device would revolutionize circuit and nanoarchitecture implementations.

3. Energy Efficiency: Energy efficiency has become the limiting factor of any beyond CMOS device using electronic charge or electric current as a computational information token used to represent a state variable. It also appears that it will be a dominant criterion in determining the ultimate applicability of alternate state variable devices. Clock speed versus density trade-offs for electron transport devices will dictate that for future technology generations; clock speed will need to be decreased for very high densities or conversely, density will need to be decreased for very high clock speeds. Nanoscale electron transport devices will best suit implementations that rely on the efficient use of multi-core processing to minimize energy dissipation.

4a. Ion/IoffRatio (Memory Devices): The Ion/Ioff ratio of a memory device is the ratio of the resistance of a memory storage element in the Ion state to its resistance in the Ioff state. For nonvolatile memories, the Ion/Ioff ratio represents the ratio between the read current of a selected memory cell to the leakage current of an unselected cell. In cross-point memories, a very large Ion/Ioff ratio is required to minimize power dissipation and maintain adequate read signal margin.

4b. Gain (Logic Devices): The internal gain of nanodevices is an important limitation for presently used combinatorial logic where gate fan-outs require significant drive current and low voltages make gates more noise sensitive. New logic and low fan-out circuit approaches will be needed to use most of these nanodevices for computing applications. Signal regeneration for large circuits of nanodevices may need to be accomplished by integration with CMOS.

5. Operational Reliability: Operational reliability is the ability of the memory and logic devices to operate reliably within their operational error tolerance given in their performance specifications. The error rate of all nanoscale devices and circuits is a major concern. These errors arise from the difficulty of providing highly precise dimensional control needed to fabricate the devices and also from interference from the local environment. Large-scale and powerful error detection and correction schemes will need to be a central theme of any architecture and implementations that use nanoscale devices.

6. Operational Temperature: Nanodevices must be able to operate close to a room temperature environment for most practical applications with sufficient tolerance for higher temperature (e.g., 100 °C) operation internal to the device structure.

7. CMOS Technological Compatibility: The semiconductor industry has been based for the last 40 years on incremental scaling of device dimensions to achieve performance gains. The principal economic benefit of such an approach is it allows the industry to fully apply previous technology investments to future products. Any alternative technology as a goal should utilize the tremendous investment in infrastructure to the highest degree possible. Furthermore, in the near term, integratability of nanodevices with silicon CMOS is a requirement due to the need for signal restoration for many logic implementations and to be compatible with the established technology and market base. This integration will be necessary at all levels from design tools and circuits to process technology.

8. CMOS Architectural Compatibility: This criterion is motivated by the same set of concerns that motivate the CMOS technological compatibility, namely the ability to utilize the existing CMOS infrastructure. Architectural compatibly is defined in terms of the logic system and the data representation used by the alternative technology. CMOS utilizes Boolean logic and a binary data representation and, ideally, an alternative technology would need to do so as well.

1.7 Selection of Nanodevices as Technology Entries

Candidate Technology Entries are identified through a variety of means including a minimum of four workshops held in each 2 year cycle, extensive literature searches, personal knowledge of ERD ITWG members, ERD critiques, and so on.

These candidate Technology Entries are considered for inclusion in the ITRS ERD chapter based on their potential for accomplishing the objectives for a new technology, level of published research activity, credibility, and progress. In addition a candidate Technology Entry should have attained significant maturity in its research domain. Its continued inclusion is governed by progress in resolving those research issues gating demonstration of feasibility.

In addition to the requirements discussed above, specific criteria for including a Technology Entry in any one of the Research Devices and Architectures sections are: (1) research on the proposed Technology Entry is published by two or more groups in archival literature and peer reviewed conferences, or (2) research on the proposed Technology Entry is published extensively by one group in archival literature and in peer reviewed conferences.

1.8 Perspectives

Development and scaling of CMOS over the past 40+ years has revolutionized many aspects of our lives and has been a driver of the world-wide economy. We communicate globally at any time using a paper-thin computer–telephone, no larger than a wallet, with the computational power far exceeding that of a dated mainframe computer. Similar hand-held devices coupled to a complex satellite network system (Global Positioning System or GPS) can locate our position with an accuracy of a few feet and can navigate us through completely unknown terrain (e.g., a large metropolitan area or an arid desert). Soon automobiles will be able to talk to each other to operate an automobile safely making the human driver obsolete. These technologies have been enabled by ever-shrinking MOSFETs providing lower cost, higher speed, and lower power dissipation per transistor in silicon-based integrated circuits. Scaling of silicon MOSFETs will likely continue to the 8 nm, and possibly even to the 5 nm technology generation, at which point individual MOSFETs will have reached their fundamental scaling limit defined by the relatively small number of atoms making up a transistor.

Given this approaching limit on physical scaling of the MOSFET structure and its properties, how can the semiconductor industry continue to provide lower cost, higher density, and higher performance ICs? In the relative short-term, the design community will continue its efforts and successes to obtain performance gains and cost savings by deriving more value from current technology. Also, some important applications can be addressed by current technology for speed, but need lower power dissipation, at a lower cost per chip (e.g., a smart cell phone). Also, More-than-Moore technology, in which current IC technology is integrated with other current technologies (e.g., sensors, RF components) on a circuit board or in a package, is being used to provide many functions for new applications.

In the longer term, a new information-processing technology, capable of providing additional scaling of the primitive element's size, cost, and power dissipation together with increased data throughput, would have invaluable impact. Undoubtedly, it would set off the discovery of another round of new applications, some opening completely new possibilities such as nanomorphic microsystems used in vivo to diagnose and attack disease cells [8].

Perhaps Kroemer had the best perspective on application of a new technology when in his Nobel Lecture he stated [9]: The principal applications of any sufficiently new and innovative technology always have been – and will continue to be – applications created by that technology.

So, as a community of pioneers seeking to discover a new information-processing technology, let us remain alert to new applications for our current findings.

Notes

1. Intel co-founder Gordon Moore's bold prediction, popularly known as Moore's Law, states that the number of transistors on a chip will double approximately every 2 years. Consequently, the number of transistors on a chip of constant area will double as the transistor's linear dimension scales down by . This scaling enables an average annual reduction of the cost per transistor of 29%.

2. The ITRS is sponsored by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Taiwan Semiconductor Industry Association (TSIA), and the United States Semiconductor Industry Association (SIA).

3. The state variable for an electron could also be its spin, its mass, or its wave function.

References

1. Moore, G.E. (1965) Cramming more components onto integrated circuits. Electronics Magazine, 38, 3–6.

2. Wikipedia (2014) http://en.wikipedia.org/wiki/Information_Age (accessed 16 January 2014).

3. Jefferies (2014) http://jefferies.com/CMSFiles/Jefferies.com/files/Insights/Moore%20Stress_Structural%20Industry%20Shift_09272012.pdf (accessed 16 January 2014).

4. Cellular News (2014) http://www.cellular-news.com/story/43209.php (accessed 16 January 2014).

5. Jorgenson, D.W., Ho, M., and Samuels, J. (2014) http://scholar.harvard.edu/files/jorgenson/files/02_jorgenson_ho_samuels19nov20101_2.pdf (accessed 16 January 2014).

6. Zhirnov, V.V., Cavin, R.K. III, Hutchby, J.A., and Bourianoff, G.I. (2003) Limits to binary logic switch scaling – A gedanken model. Proceedings of the IEEE, 91 (11), 33–36.

7. Zhirnov, V.V., Cavin, R.K. III, and Bourianoff, G.I. (2010) New State variable opportunities beyond CMOS: A system perspective, in Emerging Technologies and Circuits (eds A. Amara, T. Ea, and M. Belleville), Springer.

8. Zhirnov, V.V. and Cavin, R.K. III (2010) Microsystems for Bioelectronics: the Nanomorphic Cell, Elsevier Press.

9. Kroemer, H. in his Nobel Lecture (8 December 2000) Quasi-Electric Fields and Band Offsets: Teaching Electrons New Tricks, Aula Magna, Stockholm University.

2

What Constitutes a Nanoswitch? A Perspective

Supriyo Datta¹, Vinh Quang Diep¹, and Behtash Behin-Aein²

¹Purdue University, USA

²GLOBALFOUNDRIES Inc., USA

2.1 The Search for a Better Switch

A basic element in digital logic is a switch or an inverter comprising a pair of complementary metal oxide semiconductor (CMOS) nanotransistors (Figure 2.1a) whose resistances and change in a complementary manner in response to the input voltage Vin. As Vin changes from 0 to VDD, the resistance of the NMOS transistor gets smaller while the resistance of the PMOS transistor gets larger making the output voltage

equation

change from VDD to 0 as shown in Figure 2.1b so that the output represents an inverted version of the input.

Figure 2.1 (a) CMOS inverter comprises an NMOS transistor (R1) and a PMOS transistor (R2). (b) Input–output characteristics of the inverter

For some time now it has been recognized that one of the biggest obstacles to continued downscaling is the heat dissipated [1,2]. Every time a switch changes state, the charge stored in an input or an output capacitors gets dumped thus dissipating an energy of QVDD. If there are Nact number of active switches switching at a frequency per second, the power dissipated can be written as

(2.1) equation

To estimate the energy QVDD dissipated per switch, we could use the numbers for the Intel® Core™ i3-530 Processor taken from their Web site at http://ark.intel.com/products/46472 [3]

equation

Since the power dissipated cannot increase too much beyond 73 W we cannot increase the number of active switches Nact or their speed of operation very much, unless we discover switches that dissipate less energy without compromising the speed. It was this recognition that prompted the Semiconductor Research Corporation (SRC) together with the National Science Foundation (NSF) to launch the Nanoelectronics Research Initiative (NRI) in 2005 with the objective of exploring the possibility of realizing a better switch based on any known physical mechanism.

Outline: In this chapter we would like to share our perspective on the question of what constitutes a transistor-like switch, and how we could build one based on novel physical mechanisms and assess its performance. As an example of a radically different physical mechanism, we will focus on spintronics and nanomagnetics where there has been enormous progress in the last two decades. But we will try to phrase our discussion and conclusions in general terms so that it could be easily adapted to other phenomena as well.

The new discoveries in spins and magnets are already finding use in memory devices both to Read (R) information from magnets and to Write (W) information onto magnets. Many other new phenomena are being investigated for nanoelectronic memory as described in Part Two of this book. It seems natural to ask whether these advances in W&R units for memory devices could also translate into a new class of logic devices.

In Section 2.2 we start with a very brief and oversimplified discussion of the most common switch used to implement digital logic based on CMOS transistors stressing the key property of gain that allows us to interconnect them into complex circuits without the use of external amplifiers or clocks. To harness spins and magnets for logic applications one could either integrate them onto CMOS devices that provide the gain (see for example [4]) or try to design transistor-like spin–magnet devices having gain. It is the latter option that we will explore in this chapter.

We will argue that a CMOS switch can be viewed as an integrated W–R unit, using the word Write in a somewhat unconventional sense. The purpose is not to provide any new insight into CMOS, but to help understand how W and R units used for memory devices can be combined to build transistor-like switches.

In Section 2.3 we discuss the standard W and R devices used for magnetic memory devices and present one way to integrate them into a single unit where the input and output are electrically isolated, but we argue that such a unit would not provide the key transistor-like property of gain. We will then show (Section 2.4) that the recently discovered giant spin Hall effect (GSHE) could be used to construct a W–R unit with gain [5].

Other possibilities for transistor-like W–R units with gain are briefly discussed in Section 2.5 including all-spin logic (ASL) [6] along with new possibilities based on newly discovered phenomena. Indeed, with the growing research interest in STT-MRAM (spin transfer torque magnetic random access memory) for both stand-alone [7] and embedded memory applications [8,9] it is likely that many more new phenomena will be discovered that could be used to construct transistor-like W–R units for logic applications.

Also we should mention that there are other independent proposals like the trans-spinor [10] and m-logic [11] that could be viewed as examples of the same W–R paradigm for logic that we are discussing here.

In Section 2.6 we end with a brief discussion of how these alternative transistor-like switches could be evaluated in terms of possible applications. A key metric is the energy–delay product and we will argue that new materials and phenomena for W and R units are needed to provide any improvement over standard CMOS switches. On the other hand the nonvolatility and reconfigurability of switches based on magnets is a novel feature that could enable a whole new class of circuits very different from those currently possible.

2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain

To understand the key characteristics of a transistor-like switch it is useful to take a brief look at a standard transistor. The simplest transistor is an NMOS or a PMOS, but we choose a CMOS switch which combines the two into a single switch that performs a logic operation, namely NOT, and has an input–output characteristic resembling those obtained from the spin switches discussed later in the chapter.

A CMOS switch is made of an NMOS and a PMOS transistor, which constitute the voltage-controlled resistors and shown in Figure 2.1a. Let us briefly describe the characteristics of an NMOS and a PMOS transistor, which can then be combined to obtain the input–output characteristics of the CMOS inverter shown in Figure 2.1b.

NMOS transistor: The resistor in Figure 2.1a is an NMOS transistor whose resistance

equation

is reduced by a positive input voltage Vin. For small input voltages the conductance ( ) increases exponentially with Vin (see for example [12])

equation

Also, the resistance is not constant and ideally the current saturates for large Vout. We could describe this behavior approximately as ( : constant)

(2.2) equation

With the current saturates perfectly, which is what we would ideally like; but with we have a characteristic looking more like real transistors, with the current showing an increase with Vout due to drain-induced barrier lowering (DIBL).

PMOS transistor: The other resistor ( ) in Figure 2.1a is a PMOS transistor whose resistance is increased by a positive input voltage and we will assume that the characteristics can be described by an expression similar to Equation 2.2 but with Vin and Vout replaced by (VDD − Vin) and (VDD − Vout) respectively.

(2.3)

equation

In general the NMOS and PMOS need not be symmetric with the same constant I0 appearing in both current expressions (see Equations 2.2 and 2.3) but we will ignore such details, since our objective is to use the simplest model just to illustrate the main points.

Switch characteristics: The input–output characteristics of a CMOS inverter are obtained by solving Equation 2.2 for (NMOS) and Equation 2.3 for (PMOS) simultaneously. For any particular Vin, we adjust Vout numerically so as to make . This leads to the switch characteristics shown in Figure 2.2 for different values of the parameter reflecting different degrees of current saturation as discussed earlier.

Figure 2.2 (a) NMOS, (b) PMOS and (c) Input-output characteristics of a CMOS input–output characteristics of a CMOS inverter obtained by solving Equation 2.2 for R1 (NMOS) and Equation 2.3 for R2 (PMOS) simultaneously for different values of

Gain: A key attribute of a logic unit is its gain defined as the change in the output voltage for a given change in the input voltage

(2.4) equation

A logic unit should have a gain >1 in order to drive another in a circuit. It is evident from Figure 2.2 that while with large values of the inverter has a sizeable gain, the gain if . Our is a parameter introduced (see Equations 2.2 and 2.3) to account for the drain voltage dependence of the current and is usually far bigger than one for any real transistor. And so the situation with is not of any real practical significance.

We are simply using the factor to make the point that in order to have gain >1, one needs an input–output asymmetry whereby the current is controlled largely by Vin, and very little by Vout. This is evident if we rewrite the current in Equation 2.2 for large Vout

equation

showing that the factor represents the asymmetry in the response of the current to the input and output voltages. With , this asymmetry is lost and so is the gain.

Switch as a Write–Read pair: Before we move on, let us point out that a CMOS switch could be viewed as a Write–Read (W–R) pair, if we use the word Write in a somewhat unconventional sense. This viewpoint may seem artificial and probably does not provide any insight into the operation of CMOS switches. Our reason for introducing it is as an aid to understand how Write and Read units based on spins and magnets can be combined to form switches.

We could define the state of the complementary pair in terms of the ratio of the two resistances and :

(2.5) equation

and create two plots: the Write (W) characteristics showing as a function of the input voltage Vin (Figure 2.3a) and the Read (R) characteristics showing the output voltage Vout as a function of the state (Figure 2.3b).

Figure 2.3 (a) Write operation in a CMOS inverter: State of the CMOS pair defined as S = log(R2/R1) as a function of the input voltage Vin. (b) Read operation: Output voltage Vout as a function of the state S. (c) Symbolic representation depicting the switch as a Write–Read pair

The former describes the W operation whereby the state of the CMOS inverter is set according to the input voltage Vin, while the latter describes the R operation in that the supply voltage VDD results in an output voltage Vout depending on the state as shown symbolically in Figure 2.3c:

(2.6) equation

Note that we are stretching the meaning of the Write operation somewhat, since the state S does not persist once the input Vin has been removed: Unlike real memory devices, the Read operation needs to be carried out while Vin is present. Our purpose here is simply to connect the language of memory devices involving W and R units to that of CMOS so that we can understand and adapt the key property of gain that distinguishes logic units.

To integrate W and R into a transistor-like switch, an input–output asymmetry seems important: the gain of a CMOS switch seems intimately related to the fact that the input voltage Vin is far more effective in controlling the state of the switch than the output voltage Vout. This input–output asymmetry and the resulting gain make a transistor very different from reversible Hamiltonian systems often discussed in the context of nanoscale systems. To harness spins and magnets for logic devices we have two broad options:

Integrate them onto CMOS devices which provide the gain.

Design transistor-like spin–magnet devices that have gain.

It is the latter possibility that we are discussing in this chapter.

2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?

Since W and R units based on magnetic tunnel junctions (MTJs) are now well-known, it seems natural to ask whether these could be combined into a transistor-like switch. Before addressing that question let us briefly summarize how an MTJ-based W and R device works.

2.3.1 Operation of an MTJ

Figure 2.4a shows a simplified MTJ structure having one layer with a reference magnet separated by a tunnelling barrier from a free layer magnet of nanometre scale thickness whose magnetization represents the stored information. Figure 2.4b shows a typical resistance versus current characteristic of an MTJ taken from Kubota et al. [13] which illustrates the basic physical phenomena underlying both the R and W operations.

Figure 2.4 (a) A simplified schematic of a magnetic tunnel junction (MTJ). (b) A typical resistance versus current characteristic of an MTJ taken from Kubota et al. [13]. Reprinted by permission from Macmillan Publishers Ltd: Nature Physics, Ref. [13], copyright 2008

At low currents the resistance can have one of two values: The smaller one ( ) corresponds to the P configuration with the two magnetizations parallel: while the larger one corresponds to the AP configuration with the magnetizations anti-parallel: . This phenomenon allows one to Read the state of the free magnet relative to the fixed magnet by applying a small voltage .

On the other hand Figure 2.4b shows that at sufficiently high positive currents the free layer switches from a P to an AP configuration while at high negative currents it switches from an AP to a P configuration. This phenomenon allows one to Write information contained in the polarity of the current onto the magnetization of the free layer.

Figure 2.5 shows the basic characteristics of the Write and Read unit based on MTJ device and their symbolic operations. The Write unit converts the input current Vin into the magnetization of the free magnet, while the Read unit converts the information stored in into an output current Vout given by

(2.7) equation

where V is the supply voltage and RL is a